Memory Controller Flag-Based Page Mapping for Flash Write Speed
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Solution Overview
Problem
Existing methods for writing and reading data in rewritable non-volatile memory, such as flash memory, are inefficient when dealing with data sizes smaller than the capacity of a physical page, leading to unnecessary operations and system burden due to the need to program and read predetermined values for unused or deleted data.
Innovation Solution
A method that involves configuring memory cells with data bit and redundancy bit areas, where flags in the redundancy bit area indicate valid or invalid logical access addresses, allowing for efficient mapping and operation of physical pages to logical pages, thereby avoiding unnecessary write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If predetermined values are programmed to fill up physical pages when data size is smaller than page capacity, then the physical page structure is maintained, but unnecessary write operations and system burden increase
Solution Approach 1:
The patent extracts the status indication function from the data storage function by using the redundancy bit area to store flags that indicate whether logical access addresses are valid or invalid. This allows the system to avoid programming predetermined values to unused logical addresses, as the flags alone suffice to indicate the status of each address, thereby eliminating unnecessary write operations and improving write speed.
Solution Approach 2:
The patent changes the state representation in the redundancy bit area from storing predetermined values to storing flags with two states (valid/invalid). This parameter change allows the system to convey the same information (whether an address is usable) with less data, avoiding the need to write actual data or predetermined values to every physical address, thus reducing write operations and time.
2Productivity
If predetermined values are read from physical pages, then complete physical page reading is performed, but unnecessary read operations and data transmission occur
Solution Approach 1:
The patent performs preliminary action by reading and checking the flags in the redundancy bit area before reading the actual data from the data bit area. This preliminary check allows the system to identify which logical access addresses contain valid data and which are invalid, enabling selective reading of only necessary data. This avoids reading and transmitting predetermined values from invalid addresses, reducing unnecessary read operations and energy consumption.
Solution Approach 2:
The patent applies partial action by reading only the necessary portion of the physical page data based on the flag status. Instead of reading the entire physical page regardless of content validity, the system reads only the data corresponding to valid logical access addresses, thereby reducing unnecessary read operations and energy usage while maintaining complete functionality.
3Adaptability or versatility
If all logical access addresses are mapped to physical addresses, then complete mapping is achieved, but invalid addresses consume storage space and operations
Solution Approach 1:
The patent segments the logical address space by using flags to divide logical access addresses into valid and invalid categories. This segmentation allows the mapping system to distinguish between addresses that should be accessed and those that should be ignored, maintaining complete address mapping capability while improving operation efficiency by preventing operations on invalid addresses. The flags act as segment markers that organize the address space without requiring physical separation.
Data Source
AI summary
A method of programming memory cells for a rewritable non-volatile memory module is provided. The method includes: receiving a command which indicates performing an update operation to a logical page; and identifying valid logical access addresses and invalid logical access addresses in the logical page according to the command. The method also includes: selecting a physical page; setting flags corresponding to the valid logical access addresses in a valid state, setting flags corresponding to the invalid logical access in an invalid state; programming the flags and data belonging to the valid logical access addresses to the selected physical page based on the update operation; and mapping the selected physical page to the logical page. Accordingly, the method can effectively increase the speed of programming the memory cells.