Memory Controller Multi-Level Read Flipping Decoding
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Solution Overview
Problem
Existing memory systems face challenges in efficiently decoding data due to shifting threshold voltages caused by factors like long-term data retention and varying usage scenarios, leading to high read error probabilities that exceed the capability of error correction codes and impacting performance.
Innovation Solution
A memory system and method that involves obtaining multiple read results at different levels, using a flipping result to update error counts in check equations, and iteratively flipping bits to improve decoding efficiency, leveraging soft information from these results to enhance hard decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple read results at different levels are obtained and soft information is used to enhance hard decoding, then decoding capability and efficiency are improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary read operations at multiple different voltage levels (first read level and second read level) before the actual decoding process. By obtaining multiple read results in advance and storing them for later use, the system prepares soft information that can significantly improve decoding accuracy without requiring complex real-time analysis during the decoding phase itself.
Solution Approach 2:
The patent introduces an intermediary processing stage that generates a flipping result by comparing the first and second read results. This flipping result serves as a mediator between the raw read data and the final decoding output, providing corrected bit information that enhances the hard decoding process without requiring the system to process all possible read combinations simultaneously.
2Reliability
If multiple read results at different levels are obtained, then decoding capability is improved, but loss of time increases
Solution Approach 1:
The system performs multiple read operations at different voltage levels as preliminary actions before decoding. By batch obtaining these read results in advance and storing them for later use in the decoding process, the patent avoids the need for sequential trial-and-error reading during decoding, thereby reducing overall time loss despite the additional read operations.
3Reliability
If error correction codes are used to handle read errors, then reliability is improved, but productivity decreases due to high read error probabilities exceeding correction capability
Solution Approach 1:
The patent implements a feedback mechanism where the flipping result generated from comparing multiple read results is fed back into the decoding process. This feedback information about which bits are likely erroneous is used to correct errors during decoding, enabling the system to handle read errors that would otherwise exceed the capability of standard error correction codes and maintain high productivity.
Data Source
AI summary
Examples of the present disclosure provide a memory system and operating method thereof, storage medium. Wherein the memory system includes: a memory device including multiple memory cells, a preset number of the memory cells forming a codeword; a memory controller coupled to the memory device and configured to: obtain a first read result of the codeword at a first read level; according to the decoding failure of the first read result, obtain a second read result of the codeword at a second read level, wherein the first read level is different from the second read level; and perform decoding processing on the second read result based on the flipping result, wherein the flipping result includes information of the bits of the codeword flipped in the first read result and the second read result.