Memory Controller Free Block Management for NAND Flash
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Solution Overview
Problem
The existing memory systems face inefficiencies in writing data to NAND-type flash memory due to the mismatch between the sector size of host devices and the block/page size of nonvolatile semiconductor memory, leading to uneven data distribution and increased management table sizes, which affects writing efficiency and speed.
Innovation Solution
The implementation of a memory system with channel parallel operation elements, where each memory chip is divided into planes and banks, with a controller managing free blocks through parallel operation, allowing for efficient data management and distribution across multiple physical blocks, thereby optimizing writing efficiency and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is directly recorded in an address designated from the host apparatus, then the writing operation is simple, but the erasing processing temporally concentrates in a specific area causing uneven data distribution and increased wear
Solution Approach 1:
The patent introduces a controller as an intermediary between the host apparatus and the nonvolatile semiconductor memory. The controller manages the mapping between logical addresses from the host and physical addresses in the memory, implementing wear leveling algorithms that distribute erasing operations uniformly across different blocks. This mediator resolves the conflict by maintaining simple host operations while ensuring uniform data distribution through intelligent address translation and block management.
2Measurement precision
If a small unit of data management (page size) is used for address translation, then the data management precision is improved, but the management table size increases and cannot be housed in the main storage memory of the controller
Solution Approach 1:
The patent segments the management table into multiple smaller tables, each managing a specific portion of the address space. Instead of using a single large management table that would exceed controller memory capacity, the system divides the address translation task across multiple smaller tables that can be housed in the controller's main storage memory. This segmentation maintains fine-grained page-level management precision while keeping each individual table size manageable.
Solution Approach 2:
The patent introduces a hierarchical or multi-dimensional structure for the management system. By organizing management data across multiple dimensions (such as multiple tables, or tables with multiple levels of indexing), the system achieves fine-grained address translation capability without requiring a single excessively large table. This dimensional approach allows the controller to manage page-level precision while keeping the memory footprint of the management structure within acceptable limits.
3Quantity of substance
If the capacity of the management table is decreased, then the storage space is optimized, but the address translation speed may be reduced
Solution Approach 1:
The patent implements preliminary organization and optimization of the management tables during initialization and maintenance phases. By pre-organizing data structures, pre-calculating mapping relationships, and maintaining optimized index structures in advance, the system ensures that address translation operations can proceed quickly without requiring excessively large management tables. This preliminary preparation allows efficient address translation with reduced memory requirements.
Data Source
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AI summary
A plurality of free-block management lists for respectively managing a logical block with a same bank number, a same chip number, and a same plane number as a free block, and a free block selecting unit that selects a required number of free-block management lists from the free-block management lists to obtain a free block from the selected free-block management lists are provided, thereby improving writing efficiency.