Memory Controller GPIO Triggering for Firmware Assert Dumps

Solution Overview

Problem

Existing memory systems face difficulties in rapidly and effectively identifying and addressing firmware abnormalities due to the inability to trigger an assert dump mode when the PCI Express interface experiences faults, leading to inefficiencies in problem-solving and customer support.

Innovation Solution

Reusing a general-purpose input/output interface pin to trigger an assert dump mode by configuring it to receive a level signal, allowing for timely saving of abnormal site information even in the presence of PCI Express interface faults, thereby improving problem-solving efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the PCI Express interface is used to trigger assert dump mode, then the abnormal site information can be saved, but the system cannot effectively trigger assert dump mode when the PCI Express interface fails

Engineering Contradiction:

Improveassert dump mode triggering reliabilityVSAvoidinterface dependency

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The first pin of the general-purpose input/output interface is designed to serve multiple functions: it can receive serial communication data during normal operation and can also trigger the assert dump mode when short-circuited with the grounding pin. This multi-functionality eliminates the need to rely solely on the PCI Express interface for triggering assert dump mode, thereby improving reliability while reducing interface dependency.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If a dedicated pin is added for triggering assert dump mode, then the triggering reliability is improved, but the device complexity increases

Engineering Contradiction:

Improveassert dump mode triggering reliabilityVSAvoidinterface pin quantity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The first pin of the general-purpose input/output interface is designed to serve multiple functions: it can receive serial communication data during normal operation and can also trigger the assert dump mode when short-circuited with the grounding pin. This multi-functionality eliminates the need to rely solely on the PCI Express interface for triggering assert dump mode, thereby improving reliability while reducing interface dependency.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Device complexity

If the general-purpose input/output interface pin is reused to trigger assert dump mode, then the device complexity is reduced, but the pin configuration complexity increases

Engineering Contradiction:

Improveinterface pin quantityVSAvoidpin configuration

Core Design Contradiction:

Device complexityVSEase of operation

Solution Approach 1:

The patent extracts the assert dump mode triggering function from the PCI Express interface and assigns it to a dedicated first pin of the general-purpose input/output interface. This separation allows the pin to be configured in a first mode for receiving level signals (including short-circuit triggering) and maintains its second mode for serial communication, making the configuration manageable through mode switching while achieving functional independence.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS12625786B2Memory systems, operation methods thereof, and computer-readable storage mediums to detect an abnormality in firmware

Publication Date: 2026.05.12 YANGTZE MEMORY TECH CO LTD

AI summary

The present disclosure provides a memory system, an operation method thereof, and a computer-readable storage medium. The memory system includes: a memory device and a memory controller coupled with the memory device. The memory system includes a general-purpose input/output interface including a first pin that is configurable to receive data transmitted by serial communication. The memory controller is configured to: trigger an interruption by the first pin in response to abnormality of a firmware of the memory system during operation; and trigger an assert dump mode in response to the interruption triggered by the first pin.