Memory Controller Scheduling for Urgent Row Hammer Refresh
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in efficiently performing hammer refresh operations on intensively accessed memory cell rows, leading to potential data loss due to leakage currents and increased power consumption.
Innovation Solution
A memory controller with a row hammer management circuit and scheduler is introduced, which counts access addresses, determines intensively accessed memory cell rows, and transmits hammer addresses to the semiconductor memory device using different command protocols based on urgency, enabling efficient hammer refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hammer refresh operations are performed on intensively accessed memory cell rows, then data loss is prevented, but power consumption increases and command scheduling is degraded
Solution Approach 1:
The patent applies local quality by differentiating between two types of hammer addresses (first type and second type) and applying different command protocols to each. The row hammer management circuit identifies intensively accessed memory cell rows and classifies them into different types based on access patterns, then selectively applies refresh commands only where necessary rather than uniformly across all memory rows, thereby reducing unnecessary power consumption while maintaining data integrity for vulnerable rows.
Solution Approach 2:
The patent changes the parameter of command protocol selection based on the type of hammer address identified. By monitoring access counts and determining whether a hammer address corresponds to a first type (requiring immediate refresh) or second type (requiring delayed refresh), the system dynamically adjusts the refresh strategy, optimizing the balance between data protection and power consumption.
2Reliability
If hammer refresh operations are performed immediately on all hammer addresses, then data loss is prevented, but command scheduling performance degrades
Solution Approach 1:
The patent implements preliminary action by having the row hammer management circuit continuously monitor and count access addresses to identify potential hammer addresses before actual data loss occurs. By classifying hammer addresses into different types based on access patterns and predicting which rows are at risk, the system prepares refresh operations in advance for only the necessary rows, avoiding the need to immediately refresh all memory rows and thus maintaining command scheduling efficiency.
Solution Approach 2:
The patent applies dynamics by making the refresh command selection adaptive rather than static. The system dynamically determines whether to apply a first command protocol (for immediate refresh) or a second command protocol (for delayed refresh) based on real-time analysis of access patterns and hammer address types, allowing command scheduling to flexibly adjust to actual memory stress conditions.
3Productivity
If access addresses are monitored and counted to identify hammer addresses, then refresh operations can be targeted efficiently, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the row hammer management circuit to perform multiple functions: it monitors access addresses, counts access frequencies, identifies hammer addresses, classifies them into different types, and determines appropriate command protocols. By consolidating these functions into a single integrated circuit rather than separate components, the patent achieves efficient targeted refresh operations while minimizing the increase in overall device complexity.
Data Source
AI summary
A memory controller to control a semiconductor memory device, includes a row hammer management circuit and a scheduler. The row hammer management circuit counts each of access addresses associated with accesses to a plurality of memory cell rows of the semiconductor memory device to store counting values therein and determines a hammer address associated with at least one memory cell row which is intensively accessed among from the plurality of memory cell rows and a type of the hammer address associated with an urgency of management of the hammer address based on the counting values. The scheduler transmits the hammer address to the semiconductor memory device according to a different command protocol based on the type of the hammer address.