Hardware Firmware Layered Memory Controller Power-Loss Data Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in efficiently processing data and maintaining performance during power loss, leading to potential data loss and operational complexity.
Innovation Solution
A memory system with a controller having a hardware layer and a firmware layer, where the hardware layer checks if write data belongs to a programmable range after power loss, determines repeated logical addresses, and programs the data in a designated memory block for power-loss data protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory system processes write data through both firmware layer and hardware layer after power loss, then data integrity is improved, but operational complexity increases
Solution Approach 1:
The controller is divided into a firmware layer and a hardware layer, with each layer handling specific tasks. The firmware layer processes general write commands while the hardware layer specifically handles power-loss data protection, allowing complex operations to be segmented into manageable, specialized components that work together to ensure data integrity without overwhelming operational complexity
Solution Approach 2:
The system performs preliminary checks during normal operation to identify write data that should be protected against power loss. By pre-identifying and flagging important write data before power loss occurs, the system reduces the complexity of post-power-loss processing while maintaining data integrity, as the hardware layer only needs to process previously identified critical data
2Reliability
If the hardware layer performs comprehensive checks on write data after power loss, then data protection reliability is improved, but processing speed deteriorates
Solution Approach 1:
The firmware layer performs preliminary identification of write data that requires power-loss protection during normal operation. This pre-processing creates a filtered list of critical data that the hardware layer needs to protect, allowing the hardware layer to perform comprehensive checks only on identified data rather than all write data, thus maintaining both reliability and processing speed
Solution Approach 2:
The system extracts and separates the power-loss protection function into a dedicated hardware layer, which handles only the specific task of protecting identified write data. This extraction allows comprehensive reliability checks to be performed on a subset of data (those identified as needing protection) rather than all data, maintaining processing speed while ensuring data protection reliability for critical information
3Reliability
If the system stores protected write data in a designated memory block, then data integrity during power loss is improved, but memory device complexity increases
Solution Approach 1:
The memory device is segmented into regular memory blocks and a designated power-loss protection memory block. This segmentation allows the system to store protected write data in a specific dedicated area, ensuring data integrity during power loss while keeping the overall memory device structure organized and manageable through clear functional separation
Solution Approach 2:
The hardware layer acts as an intermediary between the firmware layer and the designated memory block. It receives identified write data from the firmware layer, performs necessary protection operations, and stores the data in the designated memory block. This intermediary role simplifies the interface between different components and reduces overall system complexity by providing a dedicated translation and coordination layer
Data Source
AI summary
A memory system includes a memory device including a first memory block used for power-loss data protection and a controller coupled to the memory device. The controller includes a hardware layer and a firmware layer. The hardware layer checks whether at least one write data entry belongs to a programmable range in the memory device after power loss occurs, determines whether a logical address associated with the at least one write data entry is repeated, and programs the at least one write data entry in the first memory block.