Memory Controller Host Delay Adjustment
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Solution Overview
Problem
In storage systems, delays occur during data read operations due to the storage device having priority over the host and internal host delays, leading to inefficiencies in data transfer and read operations.
Innovation Solution
A control method and memory controller that detect and adjust the data transfer delay time period based on detected host delay times, optimizing the data transfer delay to improve read efficiency by switching between different operational states and adjusting the delay period accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the storage device has priority over the host during data transfer, then data transfer reliability is improved, but read operation efficiency deteriorates due to large delays between read operations
Solution Approach 1:
The patent applies dynamics by making the data transfer delay time period adjustable rather than fixed. The memory controller dynamically changes the delay period based on detected host delay times, allowing the system to adapt between ensuring reliable data transfer (longer delay) and improving read efficiency (shorter delay) depending on host conditions
Solution Approach 2:
The patent changes the parameter of data transfer delay time period based on detected host characteristics. By measuring actual host delay times and adjusting the delay parameter accordingly, the system optimizes the balance between transfer reliability and read operation efficiency
2Productivity
If the data transfer delay time period is increased to accommodate host delay, then read operation efficiency is improved, but data transfer time increases
Solution Approach 1:
The patent implements feedback by detecting actual host delay times and using this information to adjust the data transfer delay time period. This closed-loop approach ensures the delay is optimized based on real host performance rather than using a conservative fixed value, reducing unnecessary time loss
3Productivity
If the host sends multiple read commands continuously, then data read throughput is improved, but the host must wait for multiple data transfer steps to complete due to host delay
Solution Approach 1:
The patent applies preliminary action by having the memory controller detect and measure host delay times in advance, before processing multiple read commands. This allows the controller to pre-calculate an appropriate delay period that accommodates host processing speed, enabling smoother command submission without excessive waiting
Data Source
AI summary
A control method of a storage device wherein a host cannot transfer a command to the storage device when the storage device transfers data to the host, after which there is a data transfer delay time period and no data is transferred to the host until a read command is received from the host, the control method comprising the steps of: detecting, by a memory controller of the storage device, a host delay time of the host each time a read command is received from the host during the data transfer delay time period; and adjusting, by the memory controller, the data transfer delay time period based on one or more of the detected host delay times.