Memory Controller Hot Data Migration for Storage Speed
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Solution Overview
Problem
As flash memory technology advances, the increasing number of bits stored in each memory cell leads to more complex voltage control, resulting in slower write, read, and erase rates, as well as lower reliability, particularly in multiple level cell (MLC) and quad-level cell (QLC) storage systems.
Innovation Solution
A memory system comprising a first storage space with a faster access rate and a second storage space with a slower access rate, where hot data from the second storage space is migrated to the first storage space, allowing for faster data retrieval and improved access performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in each memory cell increases from 1 bit to 2 bits, 3 bits, and 4 bits, then the storage capacity is improved, but the access rate deteriorates
Solution Approach 1:
The memory storage space is segmented into multiple levels: a first storage space with faster access rate (using SLC or MLC) and a second storage space with slower access rate (using TLC or QLC). This segmentation allows the system to leverage different storage technologies with different performance characteristics to resolve the contradiction between capacity and speed.
Solution Approach 2:
Different regions of the memory system are assigned different qualities (access rates). The first storage space provides high-speed access for frequently accessed data, while the second storage space provides high-capacity storage for less frequently accessed data. This local differentiation of quality allows simultaneous optimization of both speed and capacity.
2Quantity of substance
If multiple level cell (MLC) and quad-level cell (QLC) storage systems are used, then the storage capacity is improved, but the reliability deteriorates
Solution Approach 1:
The memory system is segmented into two distinct storage spaces with different reliability characteristics. The first storage space (SLC/MLC) provides higher reliability for critical data, while the second storage space (TLC/QLC) provides higher capacity for less critical data. This segmentation allows the system to maintain high reliability for important operations while achieving high capacity overall.
Solution Approach 2:
Different reliability qualities are assigned to different regions. The first storage space is optimized for reliability with fewer bits per cell, while the second storage space is optimized for capacity with more bits per cell. This local quality differentiation allows the system to achieve both high reliability and high capacity simultaneously.
3Quantity of substance
If the number of bits per memory cell increases, then the storage density is improved, but the write, read, and erase rates deteriorate
Solution Approach 1:
The storage system is divided into two segments with different density-performance trade-offs. The first storage space uses lower-density cells (SLC/MLC) for high-speed operations, while the second storage space uses higher-density cells (TLC/QLC) for capacity. This segmentation enables the system to achieve both high density and high productivity.
Solution Approach 2:
Different local regions have different quality characteristics optimized for different functions. The first storage space is optimized for speed with fewer bits per cell, while the second storage space is optimized for density with more bits per cell. This allows the system to simultaneously achieve high storage density and high write/read/erase rates.
Data Source
AI summary
Examples of the present application disclose memory systems, operation methods, and electronic apparatuses, and relate to, but are not limited to, the technical field of semiconductors. In an example, a memory system includes a memory and a controller that are coupled, wherein the memory includes a first storage space and a second storage space, and an access rate of the first storage space is greater than an access rate of the second storage space. The controller is configured to: control the memory to write first data in the second storage space to the first storage space, wherein the first data is hot data stored in the second storage space.