Memory Controller Idle Mode Segmentation for Power Reduction
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Solution Overview
Problem
Memory storage devices consume excessive power in idle mode, leading to increased overall power consumption, as existing technologies lack efficient methods to reduce electricity usage while maintaining system performance.
Innovation Solution
A memory performance optimization method that includes a memory control circuit unit with a buffer memory, which counts idle time and instructs the device to enter multiple low electricity consumption modes, disconnecting power to non-essential components and temporarily storing necessary data in the buffer memory to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the memory storage device enters idle mode to save power, then power consumption is reduced, but the electricity consumption in idle mode is still higher than necessary
Solution Approach 1:
The patent segments the idle mode into multiple sub-modes (first idle mode, second idle mode, third idle mode) with progressively lower power consumption. The controller transitions between these modes based on idle time duration, allowing the system to achieve deeper power savings by dividing the idle state into hierarchical levels rather than using a single idle mode.
Solution Approach 2:
The patent implements dynamic mode transitions where the memory storage device can switch between active mode, first idle mode, second idle mode, and third idle mode based on real-time idle time monitoring. This dynamic adjustment allows the system to optimize power consumption continuously rather than remaining static in a single idle state.
2Use of energy by moving object
If power is disconnected from components to reduce power consumption, then electricity consumption decreases, but system response time increases
Solution Approach 1:
The patent applies preliminary action by maintaining the buffer memory in the first idle mode with partial power supply, allowing it to retain cached data and mapping information. This preliminary preparation ensures that when the system needs to wake up from idle mode, the buffer memory can immediately provide data without requiring full re-initialization, thus reducing wake-up time while still achieving power savings.
Solution Approach 2:
The patent applies local quality by selectively maintaining power to specific components (buffer memory) in the first idle mode while disconnecting power from other components (memory module). This selective power maintenance allows the system to achieve power savings in non-critical components while preserving quick response capability in critical components that need to remain operational.
3Use of energy by moving object
If all power is disconnected in second low electricity consumption mode, then power consumption is minimized, but the device cannot respond to host requirements
Solution Approach 1:
The patent implements periodic action by establishing a monitoring mechanism that checks for host requests even in the third idle mode where all power is disconnected. When a host request is detected, the system periodically transitions back to the active mode or first idle mode to process the request, then returns to the low-power state. This periodic monitoring allows the system to maintain minimal awareness of host requirements while staying in deep sleep mode.
Data Source
AI summary
A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.