Memory Controller Inline ECC Scheduling via Segmented Queues
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Solution Overview
Problem
Memory controllers with inline Error Correction Code (ECC) support face performance penalties due to shared memory bandwidth and non-optimal scheduling of data and ECC transactions, leading to increased read/write turnaround penalties and page conflicts in systems with limited resources.
Innovation Solution
Implementing a shared scheduler queue that allows independent scheduling of data and ECC mode transactions, enabling flexible transaction ordering and combining partial ECC writes to avoid fixed interleaving and reduce area and time complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inline ECC is used to write or read syndrome bits using the same memory interface and memory array as application data, then ECC protection is achieved in systems with limited bus bandwidth, but memory bandwidth is shared between data and syndrome bits resulting in performance penalties
Solution Approach 1:
The patent segments the scheduling of memory transactions by introducing separate scheduler queues for data transactions and ECC transactions. This allows independent management and optimization of each transaction type, preventing ECC transactions from blocking data transactions and vice versa, thereby maintaining memory bandwidth while providing ECC protection.
Solution Approach 2:
The patent implements dynamic scheduling where the priority and allocation of memory bandwidth between data and ECC transactions can adapt based on system conditions. The scheduler can dynamically adjust the interleaving pattern and timing of ECC transactions relative to data transactions, optimizing performance rather than using fixed rigid scheduling.
2Device complexity
If fixed interleaving of data transactions with ECC transactions is used, then scheduling is simplified, but read/write turnaround penalties and page conflicts increase resulting in further degradation in performance
Solution Approach 1:
The patent divides the scheduling function into separate queues for data transactions and ECC transactions, each with its own scheduling logic. This segmentation allows complex optimization strategies to be applied independently to each queue type, achieving high performance without requiring a single complex unified scheduler.
Solution Approach 2:
The patent performs preliminary scheduling decisions by pre-allocating and managing separate queues for different transaction types. This preliminary organization allows the system to avoid ad-hoc scheduling decisions that would increase turnaround time, as transactions are already positioned in appropriate queues ready for efficient execution.
Data Source
AI summary
A memory controller includes a transaction scheduler circuit and a command queue. For each access request received by the memory controller, the transaction scheduler circuit is configured to allocate a new entry in a scheduler queue, store an access address corresponding to the access request as a data address into the new entry, generate an error correction code (ECC) address from the data address and store the ECC address into the new entry, and set a corresponding ECC mode field in the new entry to indicate whether the data address or ECC address of the new entry is to be exposed during arbitration. The transaction scheduler circuit, during an arbitration cycle, is configured to select a transaction from the scheduler queue using an exposed address of each valid entry, and is configured to provide the selected transaction to the command queue.