Memory Controller Instruction Set for Non-Interleaving Block Groups
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Solution Overview
Problem
Existing memory systems face challenges in efficiently managing program operations across non-interleaving and interleaving block groups, leading to issues with data transmission and storage, particularly in ensuring the completion of program operations without data loss or retransmission.
Innovation Solution
A memory controller with a buffer memory, an instruction set configurator, and an instruction set performer that configures and performs instructions differently based on the presence of non-interleaving and interleaving block groups, ensuring data is sequentially stored and retrieved across multiple dies using a plane interleaving scheme, and erasing data from the buffer memory upon completion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If program data is stored in buffer memory for later transmission to non-interleaving block groups, then data loss is prevented, but buffer memory capacity is consumed and operation time is extended
Solution Approach 1:
The patent applies preliminary action by transmitting first data to non-interleaving block groups before transmitting second data to interleaving block groups. This sequencing ensures that data destined for non-interleaving blocks (which require sequential programming) is prepared and transmitted first, allowing the buffer to be cleared promptly after the operation completes, thus preventing data loss while minimizing buffer occupation time.
Solution Approach 2:
The patent segments the program operation into distinct phases: first transmitting data to non-interleaving block groups, then transmitting data to interleaving block groups. This segmentation allows the buffer memory to be cleared in between these phases, preventing data loss while optimizing buffer utilization and reducing the overall time the buffer holds data.
2Reliability
If program operation is performed on non-interleaving block groups before interleaving block groups, then data loss is prevented, but operation sequence complexity increases
Solution Approach 1:
The patent applies dynamics by making the instruction set configuration adaptive based on the type of block group being programmed. The controller dynamically adjusts the instruction sequence: for non-interleaving block groups, it configures instructions to transmit data first then perform programming; for interleving block groups, it configures instructions to perform programming first then transmit data. This dynamic adaptation ensures reliable operation completion while managing instruction set complexity through context-aware configuration.
3Reliability
If buffer memory capacity is maintained for retransmission, then data loss is prevented, but buffer capacity availability is reduced
Solution Approach 1:
The patent applies continuity of useful action by ensuring that the buffer memory is continuously utilized for its primary purpose of holding program data during transmission operations. By clearing the buffer promptly after program operations complete (especially after non-interleaving block group operations), the system maintains continuous buffer availability for new data, preventing both data loss and capacity exhaustion while enabling ongoing retransmission capabilities.
Data Source
AI summary
Embodiments of the present invention include a memory controller including a buffer memory configured to store program data, an instruction set configurator configured to configure an instruction set describing a procedure for programming the program data stored in the buffer memory to target memory blocks, an instruction set performer configured to sequentially perform instructions in the instruction set and generate an interrupt at a time of completion of performance of a last instruction among the instructions, and a central processing unit configured to erase the program data stored in the buffer memory when the interrupt is received from the instruction set performer. The instruction set configurator may configure the instruction set differently according to whether a non-interleaving block group exists among the target memory blocks.