Memory Controller Interface Circuit Noise Reduction
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Solution Overview
Problem
Existing memory controller systems face challenges in efficiently managing high-speed signal transmission between non-volatile devices and controllers, particularly in reducing common mode noise and power voltage noise, which can lead to communication errors due to mismatched interface types between memory controllers and devices.
Innovation Solution
The implementation of a memory controller with a controller interface circuit that utilizes both fully differential and single-ended interconnection methods, allowing for flexible communication modes by configuring transmitters and receivers differently, thereby eliminating common mode noise and power voltage noise, and enabling seamless communication regardless of interface types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a single interconnection method is used between memory controller and device, then the interface design is simple, but common mode noise and power voltage noise cannot be effectively reduced
Solution Approach 1:
The memory controller is designed with both fully differential and single-ended interconnection capabilities, allowing it to adapt to different interface types. The controller includes multiple transmitters and receivers that can operate in different modes, enabling universal compatibility with various memory devices while reducing noise through the appropriate interconnection method for each device type.
Solution Approach 2:
The system changes the interconnection parameters (differential vs. single-ended mode) based on the specific memory device being communicated with. By adjusting the transmission mode parameter, the system optimizes noise reduction performance for different device types without requiring complete redesign of the interface circuitry.
2Object-affected harmful factors
If different interface types are used for different memory devices, then noise reduction is improved, but communication compatibility between controller and devices becomes complex
Solution Approach 1:
The memory controller is designed with both fully differential and single-ended interconnection capabilities, allowing it to adapt to different interface types. The controller includes multiple transmitters and receivers that can operate in different modes, enabling universal compatibility with various memory devices while reducing noise through the appropriate interconnection method for each device type.
Solution Approach 2:
The interface circuitry is designed to be dynamic and reconfigurable, allowing the controller to switch between different interconnection modes based on the connected memory device. This dynamic adaptation ensures optimal noise reduction performance while maintaining compatibility across different device types without requiring multiple separate controllers.
3Object-affected harmful factors
If fully differential interconnection is used, then common mode noise is reduced, but the transmission line and receiver design become more complex
Solution Approach 1:
The memory controller is designed with both fully differential and single-ended interconnection capabilities, allowing it to adapt to different interface types. The controller includes multiple transmitters and receivers that can operate in different modes, enabling universal compatibility with various memory devices while reducing noise through the appropriate interconnection method for each device type.
Data Source
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Figure 3A
AI summary
A memory controller (100) configured to control a non-volatile memory device (200) includes: a signal generator (130) configured to generate a plurality of control signals comprising a first signal and a second control signal; a core (150) configured to provide a command for an operation of the non-volatile device (200); and a controller interface circuit (110) configured to interface with the non-volatile memory device (200), wherein the controller interface circuit (110) comprises a first transmitter (111) connected to a first signal line and a second signal line; and a first receiver (113) connected to the first signal line, and the first control signal and the second control signal are respectively transmitted to the non-volatile memory device (200) through the first signal line and the second signal line.