Memory Controller Interface for NAND Flash and SDRAM
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional handheld data processing devices designed for NOR flash and SRAM memory cannot efficiently utilize NAND flash and SDRAM components due to differences in memory architecture and interface, leading to reduced processing speed and increased cost and size.
Innovation Solution
A memory interface controller that enables a processor to use NAND flash and SDRAM by caching sectors from NAND flash into SDRAM, managing data flow, and performing error correction and encryption, allowing the processor to access data as if it were from NOR flash/SRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a processor designed for NOR flash and SRAM is used with NAND flash and SDRAM, then memory density and cost are improved, but interface compatibility and processing speed deteriorate
Solution Approach 1:
The patent introduces a memory interface controller as an intermediary device between the processor and the NAND flash/SDRAM memory system. This controller translates processor memory requests into the appropriate NAND flash/SDRAM protocols, enabling compatibility without modifying the processor architecture. The controller handles sector-based access patterns and data buffering, allowing the processor to interact with NAND flash through a standardized interface similar to NOR flash.
Solution Approach 2:
The patent segments the memory access function into distinct components: the processor generates logical memory addresses, the memory interface controller translates these to physical sector addresses and manages data flow, and the NAND flash/SDRAM handles storage operations. This segmentation allows each component to operate in its optimal domain while maintaining overall system compatibility.
2Quantity of substance
If a processor designed for NOR flash and SRAM is used with NAND flash and SDRAM, then memory density and cost are improved, but processing speed deteriorates
Solution Approach 1:
The memory interface controller performs preliminary actions by pre-translating processor memory requests into NAND flash/SDRAM sector addresses before actual data transfer. It also implements data buffering and caching mechanisms that prepare data in advance, reducing the time required for actual memory operations and maintaining processing speed despite the slower NAND flash interface.
3Ease of manufacture
If sector-based NAND flash access is used instead of byte-based NOR flash, then memory cost is reduced, but software architecture complexity increases
Solution Approach 1:
The memory interface controller acts as an intermediary that abstracts the sector-based access complexity from the software architecture. It translates byte-addressable processor requests into sector-based NAND flash operations, allowing existing software to continue using simple byte-addressing while the controller handles the complexity of sector management, erasure blocks, and wear leveling in the background.
4Ease of operation
If the LCD display is connected directly to the main processor bus, then display functionality is achieved, but processing speed is reduced due to increased capacitance
Solution Approach 1:
The patent extracts the LCD display interface from the main processor bus by introducing a separate display controller. This extraction removes the capacitive load of the display from the critical processor data path, allowing the processor to operate at full speed while the display controller handles display-specific operations through a dedicated interface.
Data Source
AI summary
A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and static random access memory (SRAM) memory devices to instead operate using NAND flash and synchronous dynamic random access memory (SDRAM). The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor.