Memory Controller Interleaved Data Processing
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Solution Overview
Problem
Memory controllers face inefficiencies in processing data from multiple memory devices due to constraints that prevent successive access to the same device or memory bank, leading to 'bubbles' of idle cycles and reduced bandwidth utilization, especially in 3D-stacked DRAM architectures.
Innovation Solution
The memory controller processes data by generating chunks that alternate between requests and stores remaining portions of data when switching between memory devices, ensuring continuous processing and reducing idle cycles by interleaving requests across different memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the memory controller finishes processing remaining portions of data for requests to a first memory device before beginning to access a second memory device, then the processing is simple and sequential, but bubbles of idle cycles occur in the processing pipeline and data communication bus utilization degrades
Solution Approach 1:
The memory controller performs preliminary actions by storing identifying data of remaining portions in internal memory before switching to another memory device. This allows the controller to resume processing these remaining portions after switching, preventing idle cycles and maintaining continuous data flow through the pipeline.
Solution Approach 2:
The patent introduces a new dimension of processing by interleaving requests across multiple memory devices. Instead of processing requests sequentially from one device at a time, the controller alternates between multiple devices, utilizing the time dimension to overlap processing of different requests and eliminate bubbles in the pipeline.
2Productivity
If the memory controller alternates requests between data for a longer request and data for a request from a second memory device, then bandwidth utilization improves, but bubbles of cycles are created for accessing different memory devices on subsequent cycles
Solution Approach 1:
The patent segments requests into chunks of data that can be processed in alternating fashion. By dividing requests into manageable segments and interleaving them across multiple memory devices, the controller achieves better bandwidth utilization while managing the complexity of coordination between devices.
Solution Approach 2:
The memory controller maintains continuity of useful action by ensuring that while one request is being processed from a memory device, another request is simultaneously processed from a different memory device. This overlapping processing eliminates idle cycles and maintains continuous utilization of the data communication bus.
3Stability of the object's composition
If the memory controller enforces constraints to ensure data is accessed evenly across all memory devices, then data access balance is maintained, but the controller cannot receive new requests from a memory device to accompany remaining portions, creating processing inefficiencies
Solution Approach 1:
The internal memory of the memory controller acts as an intermediary, storing identifying data of remaining portions temporarily. This intermediary storage allows the controller to maintain even data access across memory devices while preserving the ability to efficiently process remaining portions later, bridging the gap between constraint enforcement and processing efficiency.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing data on a memory controller. One of the methods comprises obtaining a first request and a second request to access respective data corresponding to the first and second requests at a first memory device of the plurality of memory devices; and initiating interleaved processing of the respective data; receiving an indication to stop processing requests to access data at the first memory device and to initiate processing requests to access data at a second memory device, determining that the respective data corresponding to the first and second requests have not yet been fully processed at the time of receiving the indication, and in response, storing, in memory accessible to the memory controller, data corresponding to the requests which have not yet been fully processed.