Memory Controller Interleaving Arbitration Scheme
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Solution Overview
Problem
Integrated circuits face challenges in reducing dynamic latency and memory access contention among multiple cores, as existing techniques like address interleaving and arbiter-based priority management increase complexity and do not allow dynamic sequence determination.
Innovation Solution
A memory controller design that includes address decoders, system buses, and arbiters with multiplexers and priority encoders to route access requests based on address least significant bits and predetermined priority levels, allowing dynamic sequence modification to avoid starvation and reduce contention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If address interleaving is used to reduce dynamic latency, then memory access speed is improved, but memory access conflict increases when multiple cores access the same memory bank
Solution Approach 1:
The memory system is divided into multiple memory banks (first memory bank, second memory bank) that can be accessed independently. The address decoder maps contiguous addresses to different memory banks based on address bits, enabling parallel access and reducing conflicts between cores accessing different banks simultaneously.
Solution Approach 2:
An arbiter is introduced as an intermediary component between cores and memory banks. The arbiter receives access requests, determines priority levels, and manages the access sequence to memory banks, resolving conflicts when multiple cores contend for the same bank while maintaining efficient access patterns.
2Adaptability or versatility
If an arbiter with select logic circuit is used to allow dynamic access sequence determination, then access fairness is improved, but circuit complexity and area increase
Solution Approach 1:
The arbiter employs dynamic priority assignment where priority levels are not fixed but can change based on current access patterns and bank availability. The system adapts the access sequence in real-time by modifying priority levels according to the state of memory banks and pending requests, providing flexibility without requiring complex reconfiguration logic.
Solution Approach 2:
The arbiter automatically manages access sequences by monitoring bank availability and core priority levels without external intervention. The system self-adjusts the access order based on current conditions, eliminating the need for complex external select logic circuits while maintaining adaptive behavior.
Data Source
AI summary
A memory controller that implements an interleaving and arbitration scheme includes an address decoder that selects a memory bank for an access request based on a set of address least significant bits included in the access request. A core requiring sequential access to memory is routed to consecutive memory banks of the memory for consecutive access requests. When multiple cores request access to the same memory bank, an arbiter determines an access sequence for the cores. The arbiter can modify the access sequence without significantly increasing the complexity of the memory controller. The address decoder determines whether the selected memory banks are available and also whether an access request is a wide access request, in which case it selects two consecutive memory banks.