Memory Controller Interleaving Lower Upper Page Writing
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Solution Overview
Problem
Existing memory systems with multivalued flash memory devices face inefficiencies in writing performance due to the differing program times of lower and upper page writing programs, leading to increased latency and reduced data transfer rates when using memory interleaving techniques.
Innovation Solution
A memory controller that executes all N types of page writing programs for one memory cell before switching to another, optimizing the interleaving process to minimize wasted time by concurrently processing different page types across multiple chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory interleaving is used to access multiple memory chips in parallel, then data transfer rate is increased, but writing performance becomes inefficient due to differing program times of lower and upper page writing programs
Solution Approach 1:
The patent segments the writing process into distinct lower page writing programs and upper page writing programs, each with different program times. By recognizing this segmentation, the control section can manage each segment independently and optimize the interleaving strategy to accommodate the varying durations of different writing operations across multiple memory chips.
Solution Approach 2:
The control section executes preliminary actions by identifying and preparing the memory chip that will be accessed next based on the current writing operation state. This allows the system to proactively manage the interleaving sequence, ensuring that chips with shorter program times are processed first or that the next chip is ready when the current writing operation completes, thereby minimizing idle time and optimizing overall writing performance.
2Reliability
If lower and upper page writing programs are executed sequentially, then writing completeness is ensured, but latency increases due to differing program times
Solution Approach 1:
The patent implements a dynamic control strategy where the control section adjusts the execution sequence and timing of lower and upper page writing programs based on the actual program times of different memory chips. This dynamic approach allows the system to maintain writing completeness by ensuring all pages are written while minimizing latency through flexible scheduling that adapts to the varying durations of writing operations.
Solution Approach 2:
The control section maintains continuous useful action by ensuring that while one memory chip is undergoing a lower page writing program, another chip is simultaneously undergoing an upper page writing program or preparation. This continuous utilization of writing resources across multiple chips eliminates idle time and maintains progress on all writing operations without requiring sequential completion, thereby reducing overall latency while ensuring writing completeness.
Data Source
AI summary
A memory controller for performing processing for writing data in an interleaved manner and in units of pages in a semiconductor memory section made up of chip 0 and chip 1, each of the chips composed of a large number of memory cells capable of storing two-bit data in one memory cell in units of two types of pages, the memory controller including a NAND I/F with the semiconductor memory section, and a CPU configured to execute writing programs repeatedly for two types of pages in a memory cell which belongs to the chip 0 and thereafter execute writing programs into a memory cell which belongs to the chip 1.