Memory Controller Interleaving Read Without Status Checks
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Solution Overview
Problem
Existing memory controllers for nonvolatile memory devices inefficiently manage read operations due to unnecessary status checks, leading to slower performance and increased power consumption.
Innovation Solution
Implementing a memory controller that predicts the readiness of memory planes based on elapsed time since a read command, allowing it to skip status read commands and directly issue memory access commands when a threshold time is exceeded, thereby improving operational speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller checks status information before issuing memory access commands, then it can ensure data readiness and avoid errors, but it increases operation time and reduces read speed
Solution Approach 1:
The memory controller performs preliminary actions by issuing the memory access command immediately after the read command without waiting for status confirmation. The controller proactively manages the command sequence based on predetermined timing relationships, eliminating the need for intermediate status checks while ensuring data readiness through advance command coordination.
2Reliability
If the memory controller issues status read commands for each read operation, then it can accurately determine plane readiness, but it increases power consumption due to additional command processing
Solution Approach 1:
The invention extracts and removes the status read command from the necessary command sequence. By determining that status checks are redundant when commands are issued in predetermined sequences with proper timing, the controller eliminates this unnecessary operation, thereby reducing power consumption while maintaining reliable plane readiness determination.
3Device complexity
If the memory controller sequentially processes read commands for multiple planes, then it can maintain simple control logic, but it reduces overall throughput and productivity
Solution Approach 1:
The memory controller maintains continuous useful action by overlapping the execution of read operations across multiple planes. While one plane is being read, the controller can initiate or manage commands for other planes according to predetermined timing, ensuring that the controller remains continuously productive without requiring complex interleaved management logic.
4Reliability
If the memory controller waits for status confirmation before proceeding with memory access, then it can prevent premature data access, but it increases loss of time and reduces operational efficiency
Solution Approach 1:
The memory controller skips the intermediate status confirmation step by directly transitioning from issuing the read command to issuing the memory access command after a predetermined time interval. This rushing through of the status check phase eliminates unnecessary time loss while maintaining reliability through predetermined timing that ensures data readiness before access.
Data Source
AI summary
An operation method of a memory controller includes sequentially transmitting a first read command for the first plane and a second read command for the second plane to the nonvolatile memory device, transmitting a first status read command corresponding to the first read command to the nonvolatile memory device, transmitting a first memory access command corresponding to the first read command to the nonvolatile memory device based on first status information, receiving first read data that is output from the nonvolatile memory device, skipping issuing of a status read command corresponding to the second read command and transmitting a second memory access command corresponding to the second read command to the nonvolatile memory device, after receiving the first read data, and receiving second read data that is output from the nonvolatile memory device.