Memory Controller Interleaving for Power Recovery
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Solution Overview
Problem
The complexity and performance deterioration of memory systems in portable electronic devices lead to inefficiencies in data processing, particularly during power transitions, where sudden power-offs can result in incomplete program operations and require lengthy recovery times.
Innovation Solution
A memory system utilizing a controller that implements a channel interleaving scheme and memory die interleaving scheme to manage data across multiple memory blocks and dies, allowing for simultaneous sensing and recovery of pages during power-on states, ensuring quick and stable data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory system uses multiple memory dies and blocks to store data segments, then data processing capacity and reliability are improved, but system complexity increases
Solution Approach 1:
The memory system divides data into multiple segments and distributes them across different memory dies and blocks. Each segment is independently addressable, allowing parallel access and reducing the impact of failures in any single segment. The controller manages these segments through a unified namespace, presenting a simplified interface to the host while maintaining complex internal distribution for improved reliability.
2Measurement precision
If the memory system performs sequential sensing of pages across multiple memory blocks, then data accuracy is improved, but processing time increases
Solution Approach 1:
The system transitions from sequential sensing along a single dimension to parallel sensing across multiple dimensions by simultaneously accessing pages across different memory blocks and dies. The controller coordinates multi-channel operations to sense multiple pages in parallel while maintaining data accuracy through synchronized verification, thereby reducing total processing time without sacrificing precision.
3Productivity
If the memory system implements interleaving schemes across memory dies and channels, then data processing speed is improved, but control complexity increases
Solution Approach 1:
The controller pre-establishes interleaving patterns and mapping relationships between logical addresses and physical memory locations across multiple dies and channels. By preparing these access patterns in advance and caching metadata about data segment locations, the system enables rapid parallel access without real-time computation overhead, thus achieving high processing speed while managing control complexity through pre-computed access schemes.
4Reliability
If the memory system recovers from power-off by sensing all pages in super memory blocks, then data integrity is improved, but recovery time increases
Solution Approach 1:
The system extracts and prioritizes critical metadata and boot sector information from super memory blocks during recovery. By identifying and recovering essential data structures first, the system can quickly restore core functionality and present a usable state to the host, while continuing background verification of remaining pages to ensure complete data integrity without blocking the recovery process.
Data Source
AI summary
A memory system may include: a memory device including a plurality of memory dies, each die including a plurality of memory blocks, each block including a plurality of pages; and a controller suitable for performing a command operation for the memory device and storing segments of user data and metadata for the command operation in a super memory block including memory blocks of memory dies included in a first memory die group and a second memory die group among the plurality of memory dies.