Memory Controller Dynamic Interleaving for I/O Throughput

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Solution Overview

Problem

Conventional memory systems face inefficiencies in I/O throughput and operational stability due to address limitation schemes and overheads during data storage and retrieval, particularly when using multiple memory dies, which can lead to reduced performance and lifetime.

Innovation Solution

The implementation of a memory system that employs a full synchronous interleaving scheme without address limitation, allowing data to be distributed and stored across multiple memory dies based on their operational states, and a controller that dynamically manages data processing and pairing operations to optimize I/O throughput and reduce overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If an interleaving operation is performed for multiple memory dies, then I/O throughput is improved, but device complexity increases

Engineering Contradiction:
ImproveI/O throughputVSAvoidcomplexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory system performs self-managed interleaving operations where the controller automatically distributes read requests to multiple memory dies based on their operational states without external intervention. The system monitors its own status and adjusts data distribution accordingly, eliminating the need for complex external coordination while maintaining high throughput.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The memory system dynamically adjusts the interleaving strategy based on real-time operational states of memory dies. When memory dies enter idle or error states, the controller adapts the data distribution pattern to optimize throughput. This dynamic adaptation resolves the complexity-throughput tradeoff by making the system flexible rather than rigid in its operations.

Inventive Principle:
Principle #15Dynamics

2Productivity

If address limitation schemes are used during data storage, then device complexity is reduced, but I/O throughput deteriorates

Engineering Contradiction:
ImproveI/O throughputVSAvoidcomplexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the address limitation scheme from the memory system operation. By removing this constraint, the system can freely distribute data across multiple memory dies based on operational efficiency rather than address restrictions. This extraction enables higher throughput without the need for complex address management protocols.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The memory system segments read requests into multiple independent operations that can be simultaneously executed across different memory dies. Each segment can be processed independently without address limitations, allowing parallel data retrieval that significantly improves throughput while keeping individual operations simple.

Inventive Principle:
Principle #1Segmentation

3Productivity

If pairing operations are performed to optimize data processing, then I/O throughput is improved, but loss of time increases

Engineering Contradiction:
ImproveI/O throughputVSAvoidoverhead
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The memory system performs preliminary actions by pre-identifying optimal memory die assignments for read requests before data retrieval begins. The controller analyzes operational states in advance and establishes pairing operations that will maximize throughput. This preliminary planning eliminates the need for time-consuming real-time decisions during data processing, reducing overhead while maintaining high performance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pairing operations are designed to maintain continuous useful action across multiple memory dies simultaneously. By establishing parallel read operations that continue without interruption, the system eliminates idle time and waiting periods. The continuity of data retrieval operations across multiple dies ensures that throughput is maximized without significant time loss from coordination overhead.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS11327659B2Apparatus and method for improving input/output throughput of memory system
Publication Date: 2022.05.10 SK HYNIX INC
  • US11327659B2 patent drawing
  • US11327659B2 patent drawing
  • US11327659B2 patent drawing

AI summary

A memory system may include: a plurality of memory dies suitable for storing data therein; a buffer including a plurality of clusters each suitable for buffering data to be outputted to an external device; and a controller coupled to the plurality of memory dies through a plurality of channels, and suitable for: checking control information corresponding to valid clusters among the plurality of clusters, each valid cluster currently buffering data, deciding an operation margin for performing a pairing operation by calculating data processing time associated with the valid clusters based on the control information, and performing the pairing operation during the operation margin.