Memory Controller Interrupt Coalescing for Host Power State

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Solution Overview

Problem

Current memory systems, such as solid-state drives (SSDs), face challenges in reducing power consumption, particularly when connected to hosts in low power consumption states, as they often require frequent transitions from low power states to operational states, leading to increased power usage.

Innovation Solution

The memory system incorporates a controller that receives information on the host's operating state and selects appropriate parameters for interrupt coalescing, reducing the frequency of interrupt requests by combining multiple command completion notifications into a single interrupt, thereby minimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the memory system frequently transitions from low power state to operational state to respond to host commands, then the host can maintain responsive communication, but the power consumption of the memory system increases

Engineering Contradiction:

Improvehost communication responsivenessVSAvoidmemory system power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The memory system performs preliminary actions by pre-fetching data and preparing command execution sequences while in low power state. The controller maintains a command queue and pre-processes incoming commands so that when the host needs responsive communication, the system can quickly execute pre-prepared operations rather than transitioning fully to operational state for each command, thus reducing power consumption while maintaining responsiveness.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements periodic polling or scheduled transitions from low power state to operational state rather than immediately responding to every host command. By transitioning periodically or at predetermined intervals, the memory system reduces the frequency of state transitions, thereby lowering overall power consumption while still maintaining acceptable communication responsiveness with the host.

Inventive Principle:

Principle #19Periodic action

2Speed

If the memory system remains in operational state to quickly respond to host commands, then communication responsiveness is improved, but power consumption increases

Engineering Contradiction:

Improvecommand response speedVSAvoidmemory system power consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The memory system dynamically adjusts its operational state based on host activity patterns and command queues. The controller monitors host communication patterns and transitions between low power and operational states dynamically, rather than maintaining a fixed state. This dynamic adaptation allows the system to optimize the balance between command response speed and power consumption by being operational only when necessary.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system performs preliminary processing of commands and data preparation while in low power state, maintaining command queues and pre-fetching data. This allows the memory system to quickly respond to host commands without remaining continuously in operational state, as the preliminary work is already completed or partially completed before the host issues the command.

Inventive Principle:

Principle #10Preliminary action

3Use of energy by moving object

If interrupt coalescing is used to reduce interrupt frequency, then power consumption is reduced, but the latency of command completion notification increases

Engineering Contradiction:

Improvepower consumptionVSAvoidinterrupt notification latency

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The memory system implements partial interrupt coalescing by combining multiple command completion interrupts only when certain conditions are met, such as when commands are of similar type or when the host is known to be processing efficiently. This partial coalescing reduces interrupt frequency and power consumption while avoiding excessive latency by not coalescing interrupts that would significantly delay important notifications.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The interrupt coalescing mechanism dynamically adjusts its behavior based on system conditions, host activity patterns, and command characteristics. The controller monitors the state of command queues and host processing capacity, adjusting the degree of interrupt coalescing in real-time. This dynamic adjustment allows the system to optimize the balance between power consumption reduction and interrupt notification latency.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11886742B2Memory system control method for power-level state of a host via PCIe bus including receiving optimized buffer flush/fill (OBFF) messages over the PCIe bus

Publication Date: 2024.01.30 KIOXIA CORP

AI summary

According to one embodiment, a memory system is capable of being connected to a host. The memory system includes a nonvolatile memory and a controller that receives information regarding an operating state of the host. The controller controls the nonvolatile memory according to commands from the host and selects a parameter for interrupt coalescing for transmissions to the host of interrupts related to command completion notices for the commands from the host based on the information regarding the operating state of the host.