Memory Controller Cache Coherency Invalidation
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Solution Overview
Problem
In memory systems, existing technologies face challenges in acquiring commands from submission queues with low latency, particularly due to delays in updating tail pointers and executing memory barrier instructions, which affect the efficiency of command processing.
Innovation Solution
A memory system with a controller that includes an interface for maintaining cache coherency, where the controller reads the I/O submission queue before command writing, detects invalidation requests, and acquires commands based on these requests, thereby reducing latency by avoiding the need for the host to update tail pointers and execute memory barrier instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the host updates tail pointers and executes memory barrier instructions to ensure command visibility, then command processing reliability is improved, but command acquisition latency increases
Solution Approach 1:
The controller performs a preliminary read of the submission queue region before the host writes commands. This preliminary action establishes a baseline state, allowing the controller to detect command arrivals through invalidation requests rather than waiting for tail pointer updates. The read operation is performed in advance to enable faster command detection when the host subsequently writes commands to the queue.
Solution Approach 2:
Instead of the controller polling for command availability by checking tail pointer updates (traditional approach), the invention inverts the detection mechanism: the host proactively notifies the controller of command arrival through invalidation requests when cache lines are modified. This inversion transforms a passive polling system into an active notification system, reducing latency while maintaining reliability.
2Speed
If the controller continuously monitors submission queue for command arrival, then command acquisition speed is improved, but system complexity and energy consumption increase
Solution Approach 1:
The host system performs self-service by automatically generating invalidation requests when it writes commands to the submission queue. The controller does not need to actively monitor or poll the queue; instead, the host's cache coherence protocol inherently provides notification of command arrival. This eliminates the need for complex continuous monitoring mechanisms while maintaining fast command acquisition.
Solution Approach 2:
The invalidation request mechanism provides immediate feedback to the controller when the host writes commands to the submission queue. The cache coherence protocol ensures that when the host modifies cache lines containing submission queue entries, the controller is notified through invalidation requests. This feedback mechanism enables fast command detection without requiring complex continuous monitoring, as the system naturally generates notifications only when relevant events occur.
3Stability of the object's composition
If the controller reads submission queue after host writing, then cache coherency is maintained, but command processing latency increases
Solution Approach 1:
The controller performs a preliminary read of the submission queue region before the host writes commands. This read operation establishes a baseline and triggers cache coherence validation. When the host subsequently writes commands, the invalidation request mechanism ensures cache coherency is maintained while the controller can quickly detect the change without waiting for a post-write read operation, thus reducing latency while preserving coherency.
Data Source
AI summary
According to an embodiment, a memory system includes a controller which includes an interface connectable with a host with cache coherency kept. The controller is configured to: before the host writes a command to an I/O submission queue, read the I/O submission queue; after the reading, detect via the interface an invalidation request, the invalidation request being based on writing of the command by the host to the I/O submission queue; and in response to the invalidation request, acquire the command in the I/O submission queue.