Memory Controller Inverse Mapping Table Segmentation
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Solution Overview
Problem
The existing data management methods for rewritable non-volatile memory modules face inefficiencies in searching and writing data due to the time-consuming process of data merging, which occurs when the number of available physical units in the free area is low, leading to delays in command execution.
Innovation Solution
A data management method that groups logical pages into root units with entry chains to record update information, allowing for quick retrieval of valid data during the data merging process by maintaining a global random unit search table, thereby reducing search time and enhancing writing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the memory management circuit searches for valid data from the entire inverse mapping table or redundant bit area of global random unit, then data can be found, but the search time is very long, lowering system effectiveness
Solution Approach 1:
The patent segments the inverse mapping table into multiple sub-mapping tables (first inverse mapping table, second inverse mapping table, etc.) corresponding to different logical units. This segmentation allows the search to be confined to smaller, relevant portions of the table rather than searching the entire inverse mapping table, significantly reducing search time while maintaining data search accuracy.
Solution Approach 2:
The patent performs preliminary organization of data by maintaining entry chains that pre-link valid data locations for each logical unit. When data needs to be searched, the system can directly access the pre-organized entry chain for the specific logical unit, avoiding the need to search through all global random units. This preliminary action of organizing data by logical unit dramatically reduces search time.
2Reliability
If data merging process is performed to avoid exhausting physical units in free area, then data management continuity is maintained, but the process substantially extends writing command time
Solution Approach 1:
The patent segments the data merging process by identifying only the specific logical units that need merging based on the inverse mapping table. Instead of merging data from all logical units, the system performs targeted merging only for affected logical units, reducing the overall time required while maintaining data management continuity.
Solution Approach 2:
The patent performs preliminary identification of valid data locations using entry chains before the actual data merging operation. This allows the system to prepare the merging list in advance, so that when data merging is triggered, the actual data transfer can proceed efficiently without additional search time, thus reducing the extension of writing command time.
3Ease of operation
If the memory management circuit uses logical unit-physical unit mapping table to map logical pages to physical pages, then data storage is organized, but searching for valid data in global random unit becomes time-consuming
Solution Approach 1:
The patent segments the mapping structure by creating separate inverse mapping tables for different logical units and maintaining entry chains that specifically link logical pages to their valid physical page locations. This segmented approach preserves the organized storage structure while enabling fast, targeted searches within specific logical unit contexts rather than searching the entire global random unit.
Solution Approach 2:
The patent introduces entry chains as an intermediary structure between the logical unit-physical unit mapping table and the global random unit data. The entry chains act as indexes that directly point to valid data locations, serving as a mediator that translates logical addresses to physical locations without requiring a comprehensive search of the global random unit, thus maintaining storage organization while reducing search time.
Data Source
AI summary
A data management method, a memory controller and a memory storage apparatus are provided. The method includes grouping physical units of a rewritable non-volatile memory module into at least a data area and a free area. The method also includes configuring logical units for mapping to the physical units of the data area and writing update data belonging to the logical pages of the logical units orderly into the physical pages of physical units gotten from the free area. The method further includes configuring root units for the logical pages, configuring an entry chain for each of the root units and building entries on the entry chains for recording update information of the updated logical pages, wherein each of the logical pages corresponds to a root unit. Accordingly, the table size for storing the update information is effectively reduced and the time for searching valid data is effectively shortened.