Memory Controller Iterative Decoding for Concentrated Error Correction
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Solution Overview
Problem
Current memory systems face challenges in achieving high accuracy error correction, particularly when errors are concentrated in specific areas, leading to erroneous corrections and hindered decoding processes in multidimensional error correction codes.
Innovation Solution
The memory system employs an iterative decoding process using a memory controller that performs error correction on N-dimensional error correction codes, where N is greater than or equal to two, by executing first and second decoding processes with modified inputs based on previous iteration outputs, preventing erroneous corrections by storing and using decoding results from different dimensions separately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If iterative decoding is performed using previous iteration outputs as inputs, then decoding speed is improved, but erroneous corrections occur when errors are concentrated in specific areas
Solution Approach 1:
The patent segments the decoding input into two distinct sources: syndrome information (which contains error location data) and soft bit information (which contains reliability data). By separating these functions and selectively using only syndrome information for bits identified as erroneous, the system prevents propagation of erroneous corrections while maintaining iterative decoding speed benefits.
Solution Approach 2:
The patent applies local quality by treating different bits differently based on their error status. For bits identified as erroneous through syndrome decoding, only syndrome information is used as input. For non-erroneous bits, both syndrome and soft bit information are utilized. This localized approach ensures high reliability for corrected bits while maintaining overall decoding efficiency.
2Reliability
If N-dimensional error correction codes are used, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the N-dimensional error correction decoding into distinct functional components: syndrome decoding to identify error locations, and iterative soft bit decoding for non-erroneous bits. This segmentation allows the complex N-dimensional code to be handled through manageable stages, reducing implementation complexity while preserving strong error correction capabilities.
Solution Approach 2:
The patent performs preliminary syndrome decoding before the main iterative decoding process. This preliminary action identifies which bits are erroneous, allowing the subsequent iterative decoding to focus only on non-erroneous bits. This pre-processing step simplifies the overall decoding complexity by avoiding unnecessary processing of already-identified error locations.
Data Source
AI summary
A memory system includes a non-volatile memory and a memory controller. During a read operation to read data stored in the non-volatile memory as an N-dimensional error correction code, where N is two or more, the memory controller performs an error correction process on the N-dimensional error correction code iteratively, the error correction process including a first decoding process on a first decoding input to produce a first decoding output and a second decoding process on a second decoding input to produce a second decoding output. During the error correction process, upon determining that errors remaining in the second decoding output after a most recent iteration would not be correctable, the memory controller performs a next iteration using a first decoding input for the next iteration, which is a modified form of the second decoding output of the most recent iteration.