Memory Controller Keep Buffer Error Bit Reduction

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Solution Overview

Problem

Existing memory systems face challenges in reducing error bits in data read from memory devices, leading to increased probability of errors during read operations and decreased performance over time.

Innovation Solution

A memory controller and system that includes a buffer memory device with a read buffer and a keep buffer, where data with error bits greater than a preset threshold is temporarily stored in the keep buffer and subsequently transferred to a memory block, reducing error probability during subsequent read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is continuously read from memory device, then read speed is maintained, but error bits increase over time

Engineering Contradiction:
Improveread speedVSAvoiderror bit rate
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent identifies keeping data in advance by checking error bits after a first read operation, before performing subsequent read operations. This preliminary identification allows the system to prepare corrective actions (storing in keep buffer or memory block) before errors accumulate during continuous reading, thus maintaining read speed while preventing error propagation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a keep buffer as an intermediary storage between the memory device and the host. When data with excessive error bits is detected, it is transferred to the keep buffer instead of being directly returned to the host. This intermediary buffer acts as a filter that separates clean data from error-prone data, allowing the system to maintain high read speed for good data while isolating problematic data for later handling.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If error-prone data is stored in keep buffer and transferred back to memory device, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoidbuffer management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different quality treatments to different portions of data based on their error characteristics. Data with error bits below the threshold is handled through the normal fast path (read buffer to host), while data with error bits above the threshold is routed to the keep buffer for special handling. This local quality differentiation allows the system to improve reliability for only the problematic data portions without adding complexity to the entire data path.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The memory controller performs self-service by autonomously monitoring error bits in read data and automatically routing data to appropriate buffers without external intervention. The system also self-manages the keep buffer by transferring data back to memory blocks when appropriate, reducing the need for complex external buffer management mechanisms.

Inventive Principle:
Principle #25Self-service

3Reliability

If keeping data is identified and stored in keep buffer, then error correction is enabled, but read operation time increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidread operation duration
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies error correction selectively rather than universally. Only data identified as having excessive error bits (above the threshold) is subjected to the time-consuming keep buffer storage and potential rewrite operations. The majority of data with acceptable error rates follows the fast path directly from read buffer to host. This partial action approach ensures error correction capability is available when needed while minimizing the time penalty to only the problematic data portions.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12105988B2Memory controller for reducing the number of error bits in read data and memory system including the same
Publication Date: 2024.10.01 SK HYNIX INC
  • US12105988B2 patent drawing
  • US12105988B2 patent drawing
  • US12105988B2 patent drawing

AI summary

A memory system may include a memory device including a plurality of memory blocks, a buffer memory device, and a memory controller. The buffer memory device includes a read buffer configured to store the data read from the memory device and a keep buffer configured to store part of the read data. The memory controller operates to identify keeping data among data stored in the read buffer according to a number of error bits in the keeping data when it was read from the memory device, store the keeping data in the keep buffer, and remove the keeping data from the read buffer. The memory controller may store the keeping data in any one of the plurality of memory blocks based on information related to the keeping data.