Memory Controller Key Cache for Faster Nonvolatile Data Encryption

The patent extracts the key storage function from the memory controller's volatile memory and relocates it to the host's volatile memory buffer. The memory controller only retains a small key cache for frequently accessed keys, while the host manages the large key storage space. This extraction resolves the contradiction by eliminating the need for large volatile memory in the memory system while maintaining encryption security through host-managed key storage.

The patent introduces a key cache in the memory controller as an intermediary between the host's key storage and the encryption/decryption operations. The key cache stores frequently accessed keys locally, enabling fast access for common operations while the host's volatile memory buffer provides the complete key repository. This intermediary structure resolves the speed-security tradeoff by providing both fast local access and comprehensive key management.

The patent extracts the large-capacity volatile memory component from the memory system and relocates it to the host system. The memory controller is simplified to contain only essential components (processor, buffer memory, and small key cache), while the host assumes responsibility for storing the complete set of encryption keys in its volatile memory buffer. This extraction reduces memory system complexity and manufacturing cost while preserving full key management capability through host involvement.

The patent makes the host's volatile memory buffer serve multiple functions: it acts as the general-purpose memory buffer for data operations and simultaneously serves as the key storage repository for encryption operations. This multi-functionality eliminates the need for dedicated large-capacity volatile memory in the memory system, reducing overall system complexity while maintaining comprehensive key management capabilities.

The patent segments the key storage system into two parts: a small key cache in the memory controller's buffer memory for frequently accessed keys, and a large key repository in the host's volatile memory buffer. This segmentation allows the system to maintain large overall key storage capacity while providing fast access for commonly used keys through the local cache, thereby resolving the capacity-speed tradeoff.

The patent applies local quality by providing different storage characteristics for different keys based on their access patterns. Frequently accessed keys are cached in the memory controller's buffer memory for immediate local access, while less frequently accessed keys are stored in the host's volatile memory buffer. This differentiated approach optimizes access time for critical operations while maintaining overall large key storage capacity.