Memory Controller Key Caching Using Host Memory Buffer Encryption

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Solution Overview

Problem

Existing non-volatile memory systems face inefficiencies due to the requirement of a large-capacity volatile memory for storing encryption keys, leading to increased costs and performance degradation when accessing these keys.

Innovation Solution

Implementing a host memory buffer (HMB) to store encryption keys, utilizing a key cache to enhance key retrieval speed, and employing multiple encryption and decryption portions to manage keys securely and efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large-capacity volatile memory is used to store encryption keys according to the KPIO standard, then the security and encryption capability are improved, but the system cost and device complexity increase

Engineering Contradiction:
Improveencryption securityVSAvoidvolatile memory capacity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the key storage function from the memory controller's volatile memory and relocates it to the host's memory buffer. The host memory buffer, which is already allocated for the memory system, is repurposed to store encryption keys, eliminating the need for dedicated large-capacity volatile memory in the memory controller while maintaining security requirements.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The host memory buffer serves multiple functions: it acts as both the memory buffer for normal memory operations and as the key storage area for encryption. This multi-functional usage eliminates the need for separate dedicated key storage memory, reducing overall system complexity and cost while maintaining the required security capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If a large-capacity volatile memory is used to store encryption keys, then the encryption capability is improved, but the manufacturing cost increases

Engineering Contradiction:
Improveencryption capabilityVSAvoidsystem cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The host system, which already has allocated memory resources for the memory buffer, provides the key storage service using its own existing memory buffer. This self-service approach allows the memory system to utilize already-purchased host memory resources rather than requiring additional dedicated memory components, thereby reducing manufacturing costs while maintaining encryption capabilities.

Inventive Principle:
Principle #25Self-service

3Reliability

If DRAM is used to store encryption keys, then the key storage is enabled, but the key access time increases resulting in performance degradation

Engineering Contradiction:
Improvekey storageVSAvoidkey access time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The encryption keys are pre-loaded into the host memory buffer before actual encryption operations begin. The memory controller maintains a key cache that stores frequently used keys, and the host memory buffer is pre-configured with the necessary key storage space. This preliminary preparation eliminates the need for time-consuming key retrieval during encryption operations, reducing access time and preventing performance degradation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12481769B2Memory system, memory controller and operation method thereof for encrypting data stored in a nonvolatile memory
Publication Date: 2025.11.25 SK HYNIX INC
  • US12481769B2 patent drawing
  • US12481769B2 patent drawing
  • US12481769B2 patent drawing

AI summary

The present disclosure relates to a memory system capable of encrypting and storing data, and a memory controller. The memory controller may include a first interface configured to perform data communication with a first external device, a second interface configured to generate a signal for controlling an operation of a second external device and transmit the signal; and a processor configured to receive, from the first external device, a data write command to write data to the second external device, encrypt the data by using one of a plurality of keys stored in a key area provided in the first external device in response to the data write command, and then control the encrypted data to be written to the second external device.