Memory Controller L2P Mapping Updates with Adaptive Timing

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Solution Overview

Problem

Existing data storage systems face inefficiencies in updating Logical to Physical (L2P) tables due to inflexible update triggers, leading to poor performance and reliability in varying write modes, particularly in random and sequential writes.

Innovation Solution

A dynamic condition is introduced to determine L2P table updates based on the product of theoretical times for refreshing entries, allowing for flexible timing adjustments according to the specific characteristics of sequential and random writes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a fixed threshold or condition is used to determine the time of triggering an update, then the update trigger is simple to implement, but the flexibility and adaptability to different write modes (random write vs. sequential write) deteriorates

Engineering Contradiction:
Improveadaptability to different write modesVSAvoidcomplexity of update trigger mechanism
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the update trigger condition adaptive rather than fixed. The controller dynamically adjusts the trigger threshold based on the detected write mode (sequential or random), allowing the system to optimize L2P table update timing for different workload characteristics. This resolves the contradiction by enabling high adaptability through dynamic parameter adjustment while maintaining relatively simple implementation through mode detection and conditional logic.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of update trigger threshold based on write mode. When sequential write is detected, a first threshold is used; when random write is detected, a second threshold is used. This parameter change allows the system to adapt to different write patterns, improving versatility while keeping the mechanism simple through straightforward parameter switching based on mode identification.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the L2P table is updated frequently to ensure data accuracy, then the reliability of data processing improves, but the update time and latency increase

Engineering Contradiction:
Improvereliability of data processingVSAvoidL2P table update time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by updating the L2P table selectively rather than continuously. The update operation is triggered only when specific conditions are met (based on write mode and threshold comparisons), avoiding unnecessary updates. This reduces update time and latency while maintaining reliability by ensuring updates occur at appropriate moments when data accuracy requirements are met.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent implements periodic-like action through threshold-based triggering. Instead of continuous updating, the system monitors write operations and triggers updates periodically when accumulated changes reach the dynamically determined threshold. This approach balances reliability (ensuring updates occur when needed) with time efficiency (avoiding excessive frequent updates).

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS12360915B2Operation method of controller, controller, and memory system
Publication Date: 2025.07.15 YANGTZE MEMORY TECH CO LTD
  • US12360915B2 patent drawing
  • US12360915B2 patent drawing
  • US12360915B2 patent drawing

AI summary

In an example operation method of a controller, a mapping relationship of translation from a first physical block address into a first logical block address is written to a first entry according to a write instruction. The first physical block address is a storage address in a memory, and the first logical block address is a storage address recorded in the write instruction. Storage data is written to the first physical block address. A mapping relationship of translation from the first logical block address into the first physical block address is written to a second entry. When a product of first time and second time is greater than or equal to a first value, the second entry is updated into the memory, wherein the first time is theoretical time for refreshing the first entry, and the second time is theoretical time for refreshing the second entry.