Memory Controller Data Lane Integrity Test via Signal Reflection
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Solution Overview
Problem
The existing memory system boot process is significantly delayed due to the time-consuming DIMM training process, which often detects defective data lanes late in the process.
Innovation Solution
A memory system with a memory controller that includes a memory interface with bidirectional data lanes and an AND gate, where a high signal pulse is driven on each lane to detect defective lanes by analyzing reflection timing, allowing for early identification and prevention of training on defective lanes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller performs the complete DIMM training process to optimize data lane performance, then the reliability of data transmission is improved, but the system boot time is significantly increased
Solution Approach 1:
The patent applies preliminary action by performing a quick reflection-based integrity test on data lanes before executing the complete DIMM training process. This preliminary test uses a driver to send a signal and a receiver to detect reflections, quickly identifying defective lanes so that the time-consuming training process can be skipped for those lanes, thereby reducing overall boot time while maintaining reliability for functional lanes
Solution Approach 2:
The patent extracts the integrity testing function from the complete DIMM training process. By separating the reflection-based integrity test as an independent preliminary step, the system can identify and exclude defective data lanes before committing resources to the full training sequence, thus removing unnecessary time expenditure on lanes that will ultimately fail
2Loss of time
If the memory controller uses a quick reflection-based test to detect defective data lanes early, then the system boot time is reduced, but the complexity of the testing mechanism is increased
Solution Approach 1:
The patent applies self-service by using the existing driver and receiver components already present in the memory interface to perform the reflection-based integrity test. The driver sends the test signal and the receiver detects reflections, utilizing existing hardware resources rather than introducing completely new test equipment, thereby minimizing additional complexity while achieving quick defect detection
3Reliability
If the memory controller performs complete training on all data lanes, then all potentially functional lanes are optimized, but defective lanes consume unnecessary training time
Solution Approach 1:
The patent performs preliminary integrity testing using reflection detection before committing to the complete training process. This allows the system to identify defective lanes in advance and exclude them from training, ensuring that training resources are concentrated only on potentially functional lanes, thereby improving overall training efficiency while maintaining optimization for lanes that pass the integrity test
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time required to identify defective interconnects between memory DIMMs and controllers, thereby accelerating the system boot process by enabling immediate detection and skipping the training of defective data lanes.
Implementation Method 1
driving a high signal pulse onto each of a plurality of data lanes of a memory interface, receiving a reflection of the high signal pulse on each of the data lanes
Data Source
AI summary
A memory system for a computer is provided as well as a method for integrity testing a memory interface. The memory system includes a memory controller providing a memory interface including a plurality of data lanes, wherein each of the plurality of data lanes includes a driver and a receiver, and wherein each receiver has an output. The memory system further includes an AND gate having an output and a plurality of inputs, wherein the output of each receiver is coupled to one of the plurality of inputs of the AND gate. The method includes driving a high signal pulse onto each of a plurality of data lanes of a memory interface, receiving a reflection of the high signal pulse on each of the data lanes, and determining whether the reflections received on the data lanes indicate that any one or more of the data lanes is defective.