Memory Controller Last Successful Read Voltage Level
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Solution Overview
Problem
Memory sub-systems face increased bit error rates due to temporal voltage shifts caused by slow charge loss, leading to inaccurate read operations as voltage offsets become outdated over time, resulting in read errors.
Innovation Solution
The memory sub-system controller applies the last successful read voltage level to subsequent read operations for blocks within a family, which is determined through error correction flows and stored for future use, ensuring accurate data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the memory sub-system uses fixed voltage offsets for read operations, then the initial read accuracy is maintained, but bit error rates increase over time due to temporal voltage shifts
Solution Approach 1:
The patent implements dynamic voltage offset adjustment by transitioning from fixed voltage offsets to time-dependent voltage offsets. The controller updates voltage offsets based on elapsed time since programming and temperature conditions, allowing the read voltage to adapt to temporal voltage shifts caused by slow charge loss. This dynamic adjustment maintains read accuracy over time while reducing bit error rates.
Solution Approach 2:
The patent changes the voltage offset parameter based on temporal conditions. Specifically, the read voltage offset is adjusted as a function of time elapsed since programming and temperature variations. This parameter change allows the system to compensate for voltage drift over time, maintaining measurement precision while improving reliability.
2Measurement precision
If the memory sub-system performs frequent voltage calibration, then read accuracy is maintained, but operation latency increases
Solution Approach 1:
The patent implements periodic voltage calibration rather than continuous calibration. The controller performs voltage offset updates at scheduled intervals based on time elapsed since programming and temperature changes. This periodic approach maintains read accuracy while minimizing interruptions to normal read operations, thereby reducing latency compared to continuous calibration methods.
Solution Approach 2:
The patent performs preliminary voltage calibration during manufacturing and initial programming phases. By establishing baseline voltage offsets in advance and only performing updates when necessary (based on time and temperature thresholds), the system maintains read accuracy without requiring frequent calibration interrupts, thus reducing operation latency.
3Reliability
If the memory sub-system applies time-dependent voltage offsets, then bit error rates are reduced, but device complexity increases
Solution Approach 1:
The patent implements feedback mechanisms where the controller monitors time elapsed since programming and temperature conditions, then adjusts voltage offsets accordingly. This feedback loop automatically compensates for temporal voltage shifts without requiring complex external intervention. The feedback-based approach reduces bit error rates while keeping the control logic manageable through automated decision-making based on monitored parameters.
Solution Approach 2:
The memory sub-system performs self-calibration by automatically adjusting its own read voltage offsets based on internal timing and temperature sensors. This self-service capability eliminates the need for external calibration equipment or complex manual intervention, reducing device complexity while maintaining improved reliability through time-dependent voltage adjustment.
Data Source
AI summary
An example method of performing read operation with respect to a memory device comprises: receiving a request to perform a read operation with respect to a memory page of a memory device; identifying a block family associated with a block comprising the memory page; determining a block family-based read voltage level associated with the block family; performing, using the block family-based read voltage level, a read operation with respect to the memory page; determining, by performing an error correction operation with respect to the memory page, a new read voltage level associated with the block family; and associating, by a last successful read voltage level memory data structure, the new read voltage level as a last the successful read voltage level with the block family.