Memory Controller Latency Adjustment for Defective Cells
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Solution Overview
Problem
As memory device capacity increases, it becomes challenging to fabricate devices without defective memory cells, leading to unrepaired cells that render the device unusable and result in abandonment.
Innovation Solution
A memory system with a memory controller that sets different control latencies for memory devices with unrepaired defective cells, allowing the system to continue functioning by mapping these cells to normal cells and adjusting address and command signals accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device capacity is increased, then storage capability is improved, but the likelihood of defective memory cells increases
Solution Approach 1:
The patent changes the control latency parameter for memory devices with unrepaired defective cells, setting it to a value different from normal memory devices. This allows the memory controller to distinguish and properly handle commands for devices with defects, enabling continued operation despite high defect rates that would normally occur with increased capacity.
2Device complexity
If unrepaired defective memory cells are present, then device complexity is reduced (no repair needed), but the device becomes unusable
Solution Approach 1:
The patent introduces a distinctive control latency parameter for memory devices containing unrepaired defective cells. This parameter change enables the memory controller to identify and appropriately manage commands directed to such devices, allowing them to remain usable despite having defective cells that were not repaired through traditional redundancy methods.
3Reliability
If control latency is set differently for memory devices with unrepaired defective cells, then the memory controller can recognize and handle these devices, but control signal complexity increases
Solution Approach 1:
The patent applies a localized parameter change by setting a specific control latency value only for memory devices with unrepaired defective cells, while normal memory devices continue to use the standard latency value. This localized differentiation allows the memory controller to properly handle defective devices without complicating the control signals for the entire memory system.
Data Source
AI summary
A memory system includes: a plurality of memory devices, one of which includes an unrepaired defective memory cell; a control bus that is shared by the plurality of the memory devices; a plurality of data buses assigned to each of the plurality of the memory devices; and a memory controller that communicates with the plurality of the memory devices through the control bus and the plurality of the data buses, a control latency of the memory device including unrepaired defective memory cells is set differently from a control latency of the other memory devices, where the control latency is used for recognizing control signals of the control bus.