Memory Controller Latency Feedback for Uniform Performance

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Solution Overview

Problem

Existing memory systems face challenges in maintaining uniform performance, particularly in sustain states where command processing delays can occur due to limited storage space, leading to unpredictable response times for hosts.

Innovation Solution

A memory system with a memory controller that includes a latency monitoring component to track over-latency occurrences and a completion response controller to determine a target latency based on these occurrences, thereby delaying completion responses to commands and maintaining consistent performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If wear leveling or garbage collection is performed to efficiently use memory device storage space, then memory device efficiency is improved, but command processing delay occurs leading to non-uniform performance

Engineering Contradiction:
Improvememory device efficiencyVSAvoidperformance uniformity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The memory controller monitors latency information from completed commands and uses this feedback to dynamically adjust the completion response timing for subsequent commands. The controller counts over-latency occurrences and modifies response delays based on this feedback, creating a closed-loop system that adapts to actual performance conditions and maintains uniform perceived latency despite internal processing variations

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The completion response timing is made dynamic rather than fixed. The memory controller adjusts the completion response delay based on monitored latency patterns and current operational state, allowing the system to adapt its timing characteristics in real-time to maintain uniform performance across different workloads and memory states

Inventive Principle:
Principle #15Dynamics

2Reliability

If completion responses are delayed to maintain uniform performance, then performance predictability is improved, but response time increases

Engineering Contradiction:
Improveperformance predictabilityVSAvoidresponse time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system changes the latency parameter dynamically based on monitored conditions. Rather than using a fixed completion response delay, the controller adjusts the delay parameter according to observed latency patterns and over-latency counts, optimizing the balance between uniformity and responsiveness under different operational conditions

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12236092B2Memory system for controlling latency and method of operating the same
Publication Date: 2025.02.25 SK HYNIX INC
  • US12236092B2 patent drawing
  • US12236092B2 patent drawing
  • US12236092B2 patent drawing

AI summary

Provided herein may be a memory system and a method of operating the same. A memory controller may include a latency monitoring component configured to generate information about a number of occurrences of over-latency exceeding a preset reference latency among latencies each indicating a time amount required from a time point at which first command is received from an external device to a time point at which a completion response to the first command is transmitted to the external device during a first period, and a completion response controller configured to determine a first target latency based on the information about the number of occurrences of over-latency, and provide, during a second period following the first period, the external device with a completion response to a second commands provided from the external device after the first target latency has elapsed.