3D Memory Controller Layered Error Patrol
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In three-dimensional random access memory (RAM) systems, single bit errors caused by neutron beams or similar influences can progress to multi-bit errors before detection and correction, leading to system failures due to the time it takes to detect and correct errors across multiple layered memory chips.
Innovation Solution
An information processing device with a memory module that includes a memory controller capable of prioritized patrol operations, where the controller inspects data, corrects single bit errors, and determines inspection areas based on error locations across multiple layers, performing diagnostic access to prevent multi-bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips are mounted in multiple layers to increase storage capacity, then the storage capacity is improved, but the time required to detect and correct errors increases
Solution Approach 1:
The patent performs preliminary error detection and correction actions by executing patrol operations that proactively scan memory regions. When a single-bit error is detected, the system immediately corrects it and performs targeted patrol operations on corresponding regions in other layers before multi-bit errors can develop, thus preventing time loss from undetected errors propagating across multiple layers.
Solution Approach 2:
The patent segments the error detection and correction process into targeted patrol operations for specific memory regions rather than scanning entire memory spaces. By dividing the memory into regions and using error location information to guide patrol operations, the system reduces the time required for error detection while maintaining comprehensive coverage across multiple layers.
2Reliability
If comprehensive patrol operations are performed across all memory regions to ensure error detection, then the reliability is improved, but the processing time increases
Solution Approach 1:
The patent applies local quality by performing patrol operations with different priorities and intensities in different memory regions. Regions identified as having single-bit errors receive immediate and intensive patrol attention, while other regions receive standard monitoring. This localized approach ensures high reliability for critical regions without sacrificing overall processing speed.
Solution Approach 2:
The patent implements partial action by performing patrol operations only on memory regions where errors are likely to occur or have been detected, rather than uniformly scanning all regions. The system uses error location information to determine which regions require patrol, applying excessive action (intensive patrol) only where necessary to maintain reliability while preserving processing speed in error-free regions.
3Reliability
If single bit errors are corrected immediately upon detection, then the reliability is improved, but the system complexity increases
Solution Approach 1:
The patent implements self-service by enabling the memory system to automatically detect and correct single-bit errors without external intervention. The error correction mechanism operates autonomously, using parity bits and patrol operation results to identify and correct errors, thereby maintaining high data integrity while avoiding the complexity of manual error management systems.
Data Source
AI summary
An information processing device includes: a processor that executes processing of data; and a memory module that includes a first memory in which a plurality of memory chips each storing the data are mounted in layers, and a memory controller that controls the first memory, wherein the memory controller: inspects the data; executes correction processing of the data when a single bit error is detected; determines, when a single bit error is detected in a memory chip corresponding to a first layer, a first inspection area in a memory chip corresponding to another layer, based on a first location at which the single bit error occurs; and executes first inspection of data in the first inspection area.