Memory Controller LDPC Encoding for Variable-Length Codewords
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Solution Overview
Problem
The reliability of data storage in memory systems, such as flash memory, is compromised due to internal noise and channel variations causing threshold voltage distribution abnormalities, leading to data read and write errors.
Innovation Solution
Implementing a memory system with an integrated controller that utilizes an encoding circuit and decoding circuit to apply Low-Density Parity-Check (LDPC) technology for error correction, using generator and check matrices to generate and verify encoded codewords, ensuring data accuracy through check bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction methods are used, then data storage reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent applies LDPC coding with variable code rates (e.g., 5/6, 4/6, 3/6, 2/6, 1/6) to adaptively change the encoding parameters based on channel conditions and storage requirements. This allows the system to optimize between reliability and complexity by selecting appropriate code rates rather than using fixed traditional methods
Solution Approach 2:
The patent segments the data into codewords of specific lengths (e.g., 6480 bits, 5400 bits, 4320 bits, 2160 bits, 1080 bits) and applies different LDPC coding schemes to different segments. This segmentation allows flexible error correction tailored to different data sizes and reliability requirements, reducing overall system complexity
2Measurement precision
If LDPC encoding is applied to data with different information bit lengths, then data accuracy is improved, but encoding time and latency increase
Solution Approach 1:
The patent pre-calculates and stores encoding vectors and check matrices for different LDPC code rates and codeword lengths. This preliminary preparation allows the encoding process to proceed efficiently without real-time complex calculations, reducing encoding latency while maintaining data accuracy
Solution Approach 2:
The patent dynamically selects encoding parameters (code rate, codeword length, encoding vectors) based on the input data characteristics and channel conditions. This dynamic adaptation optimizes the balance between encoding time and data accuracy for different scenarios
3Reliability
If check bits are generated and stored for every codeword, then error detection capability is improved, but memory space requirements increase
Solution Approach 1:
The patent varies the check bit length relative to information bit length by changing the code rate. For example, at code rate 5/6, check bits are 1/6 of the total codeword length, while at code rate 1/6, check bits are 1/2 of the total. This parameter adjustment optimizes the balance between error detection capability and memory space usage
Data Source
AI summary
The present disclosure provides memory systems and methods of operating memory systems. An example memory system includes a memory and a controller. The memory is coupled with the controller. The controller is configured to: receive to-be-encoded data; acquire a check code vector of the to-be-encoded data based on the to-be-encoded data, wherein the check code vector is used for an accuracy check of the corresponding to-be-encoded data; and store an encoded codeword into the memory, wherein each encoded codeword includes the to-be-encoded data and the check code vector corresponding to the to-be-encoded data, and different encoded codewords corresponding to the to-be-encoded data with different numbers of information bits have different numbers of information bits.