Memory Controller Line-Level Sparing Logic
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Solution Overview
Problem
Current memory sparing techniques provide only gross, low-resolution backup, wasting resources by allocating entire unused memory ranks as spares, even though individual failing ranks may have billions of operative bits, and do not allow for line-specific failure management.
Innovation Solution
A memory controller is equipped with detect logic to identify failing memory lines and store specific memory sparing information, allowing for line-specific redirection of access requests to spare memory lines, reducing resource waste and improving sparing resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory sparing is implemented at the rank level by allocating entire unused memory ranks as spares, then memory reliability is improved, but resource utilization deteriorates due to allocation of entire ranks even when only a few bits have failed
Solution Approach 1:
The patent segments the memory hierarchy into multiple levels: rank level, bank level, and line level. Instead of treating entire memory ranks as atomic units for sparing, the system divides ranks into banks and further into lines, enabling granular identification and sparing of only the specific failed lines while preserving the rest of the memory rank for use.
Solution Approach 2:
The patent implements local quality by applying different sparing strategies to different portions of memory based on their actual condition. Rather than uniformly sparing entire ranks, the system identifies specific failed lines within ranks and applies sparing only to those local regions, allowing healthy portions of memory to continue operating at full capacity.
2Reliability
If unused memory ranks are allocated as spare ranks, then coverage for future failures is improved, but power consumption and resource waste increase
Solution Approach 1:
The patent implements dynamic sparing where the spare memory configuration is not fixed but adapts based on actual failure patterns. The system continuously monitors memory health and dynamically reconfigures which lines are active versus spared, allowing the memory system to optimize between reliability and resource usage based on current conditions rather than static pre-allocation.
Solution Approach 2:
The patent changes the granularity parameter of memory sparing from rank-level to line-level. This parameter change enables the system to spare only the minimum necessary memory resources (individual failed lines) rather than large fixed blocks (entire ranks), thereby reducing power consumption and resource waste while maintaining adequate failure coverage.
3Device complexity
If memory sparing is done at the rank level with track switch between ranks, then simplicity of implementation is maintained, but precision of failure addressing deteriorates to low-resolution sparing
Solution Approach 1:
The patent applies the nested doll principle by creating a hierarchy of memory organization where lines are nested within banks, which are nested within ranks. This nested structure allows the system to maintain the simple rank-level interface while internally implementing more granular line-level sparing, achieving high precision without proportionally increasing external complexity.
Solution Approach 2:
The patent adds another dimension to the memory addressing hierarchy by introducing bank-level organization between rank and line. This additional dimensional layer enables more precise failure localization and sparing while maintaining compatibility with existing rank-level memory interfaces, effectively increasing resolution without fundamentally changing the external system architecture.
Data Source
AI summary
Techniques for implementing memory sparing with a memory controller. In an embodiment, a memory controller stores memory sparing information which is specific to a first line of memory in a memory coupled to and controller by the memory controller. In another embodiment, the memory controller includes a second memory line which is to operate as a spare for the first line of memory, where accessing the second memory line is to be a substitute for accessing the first memory line.