Memory Controller ECC Using Linear Operations for NAND Read Errors
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Solution Overview
Problem
NAND flash memory devices face challenges in error correction due to threshold voltage dispersion and resource-intensive soft decision decoding, which increases decoding latency and resource usage.
Innovation Solution
Implementing a memory controller with an ECC circuit that uses linear operators to generate and process parity bits and reliability information from multiple read data sets, reducing resource usage while maintaining high error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft decision decoding is used to correct error bits, then error correction capability is improved, but resource usage and decoding latency increase
Solution Approach 1:
The patent segments the error correction process into two distinct stages: first hard decision decoding is performed using minimal resources, and only if that fails, soft decision decoding is initiated. This segmentation allows the system to achieve high error correction capability when needed while avoiding the resource overhead of always using soft decision decoding.
Solution Approach 2:
The patent performs preliminary hard decision decoding before attempting soft decision decoding. This preliminary action filters out many error cases that can be corrected with minimal resources, preventing the need to always engage the more resource-intensive soft decision decoding mechanism.
2Reliability
If soft decision decoding is used when hard decision decoding fails, then error correction capability is improved, but decoding latency increases
Solution Approach 1:
The patent implements a periodic two-stage decoding process where hard decision decoding is performed first in all cases, and soft decision decoding is periodically applied only when the hard decision decoding fails to correct errors. This periodic application of the more time-consuming soft decision decoding reduces average decoding latency while maintaining high error correction capability when needed.
Data Source
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AI summary
An operating method of a memory controller is provided. The operating method includes receiving a first read data (e.g. codeword) and a second conversion information, the second conversion information including data obtained by converting a second read data based on a linear operation (e.g. syndrome former), and the first read data and the second read data including data read from same memory cells; converting the first read data based on the linear operation to generate a first conversion information; performing a logical operation (e.g. XOR or XNOR) on the first conversion information and the second conversion information to generate an operation information; performing an inverse operation of the linear operation (e.g. Berlekamp-Massey algorithm and Chien search) on the operation information to generate a reliability information; and correcting an error of the first read data based on the first read data and the reliability information.