Memory Controller Linked List Scheduling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computing systems, deep input queue circuits in memory controllers lead to longer arbitration times and reduced memory bandwidth utilization due to the difficulty in quickly traversing large numbers of memory access requests, which existing technologies fail to efficiently address.
Innovation Solution
Implementing linked lists to manage memory access requests, where read requests are ordered by age and scheduled using head pointers, allowing for efficient arbitration and prioritization, and enabling the skipping or relinking of requests to maintain progress and ensure desired quality-of-service levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If deep input queue circuits are used to store memory access requests, then the memory controller can handle more requests, but the arbitration time increases and memory bandwidth utilization decreases
Solution Approach 1:
The patent divides the input queue into multiple separate queues (e.g., queue 0, queue 1, queue 2, queue 3) instead of using a single deep queue. Each queue stores a limited number of requests (e.g., 4 requests per queue), and the system uses round-robin arbitration to select which queue to service next. This segmentation reduces the maximum depth of any individual queue, thereby limiting the maximum arbitration time needed to service requests while still maintaining the ability to handle a large total number of requests across all queues.
2Quantity of substance
If deep input queue circuits are used to store memory access requests, then the memory controller can handle more requests, but memory bandwidth utilization decreases
Solution Approach 1:
The patent implements dynamic queue selection and management where the arbitration logic can adaptively choose which queue to service based on current system state. The round-robin mechanism ensures that the system dynamically rotates through different queues, preventing any single queue from becoming a bottleneck and ensuring continuous utilization of memory bandwidth. This dynamic approach allows the system to maintain high bandwidth utilization even when handling large numbers of requests.
3Device complexity
If traditional arbitration methods are used to select memory access requests, then simplicity is maintained, but efficiency and quality-of-service levels decrease
Solution Approach 1:
The patent incorporates feedback mechanisms where the arbitration logic monitors the state of multiple queues and uses this information to make intelligent scheduling decisions. The round-robin counter provides feedback about which queue was last serviced, enabling the system to systematically rotate through queues and ensure fair resource allocation. This feedback-driven approach improves scheduling efficiency and quality-of-service without requiring complex priority arbitration logic.
Data Source
AI summary
A memory controller circuit coupled to multiple memory circuits may receive a read request for a particular one of the memory circuits and insert the read request into one of multiple linked lists that includes a linked list whose entries correspond to previously received read requests and are linked according to respective ages of the read requests. The memory controller circuit may schedule the read request using a head pointer of one of the multiple linked lists.