Memory Controller Linked-List Scheduling for Write Merging
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Solution Overview
Problem
Existing memory controller systems require age-based matrices for scheduling and independently handle read and write commands, lacking the ability to convert memory cycles and support write merging and read snarfing, which limits performance and power efficiency.
Innovation Solution
A memory controller system with a scheduling module, data buffer, global order buffer, and linked-list controlling module that facilitates age and priority-based scheduling, enables seamless conversion between read and write cycles, and supports controller-based caching and atomic operations by processing commands based on dependencies to trigger write merging and read snarfing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If age-based matrix scheduling is used to manage read/write commands, then scheduling order is maintained, but device complexity increases and performance is limited
Solution Approach 1:
The patent extracts the complex age-based matrix scheduling mechanism and replaces it with a simplified linked-list data structure. The linked-list controlling module maintains scheduling order through sequential node pointers rather than requiring a comprehensive age-based matrix, thereby reducing device complexity while preserving productivity.
Solution Approach 2:
Instead of using a traditional matrix structure where rows and columns represent age and command types, the patent inverts the approach by using a linked-list structure where nodes represent commands and pointers represent scheduling order. This inversion simplifies the data structure while maintaining the necessary scheduling functionality.
2Adaptability or versatility
If read and write commands are handled independently, then command processing is simple, but the ability to convert memory cycles and support write merging/read snarfing is lost
Solution Approach 1:
The linked-list controlling module serves multiple functions: it schedules commands, detects dependency hits, triggers write merging, and enables read snarfing. This universal module handles both read and write commands through the same data structure, providing adaptability for memory cycle conversion without proportionally increasing device complexity.
Solution Approach 2:
The system performs preliminary dependency checking by comparing incoming commands with existing linked-list nodes before execution. This preliminary action identifies opportunities for write merging and read snarfing early in the command pipeline, enabling adaptive memory cycle conversion without requiring complex real-time processing.
3Productivity
If multiple separate queues are used for different command types, then command organization is improved, but the number of commands increases and performance is limited
Solution Approach 1:
The patent merges multiple separate command queues into a single unified linked-list structure. By combining read commands, write commands, and dependency-tracking into one data structure, the system reduces the total number of command objects while improving processing throughput through unified scheduling and opportunistic command consolidation.
4Loss of energy
If DRAM operations are scheduled to reduce latency and power consumption, then energy efficiency is improved, but the ability to optimize through write merging and read snarfing is lost
Solution Approach 1:
The linked-list controlling module implements feedback mechanisms by continuously monitoring command dependencies and triggering write merging or read snarfing operations when dependency hits are detected. This feedback loop optimizes both energy efficiency and performance by dynamically adjusting command execution based on actual system state rather than following fixed scheduling patterns.
Data Source
AI summary
A memory controller system comprising a scheduling module, a data buffer module, a global order buffer module and a linked-list controlling module. The linked-list controlling module is configured to receive and process a first command comprising a write command or a read command. The linked-list controlling module constructs at least one linked-list head based on scheduling dependencies and determines whether the first command is dependency-hit by comparing the first command with the existing commands buffered in the global order buffer module. If the first command is dependency-hit, the linked-list controlling module is configured to trigger a write merging process or a read snarfing process.