Memory Controller ECC Using Shift Reads and LLR Correction
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Solution Overview
Problem
Existing memory systems face challenges in efficiently correcting errors in data read from semiconductor memory due to variations in threshold voltage distributions of cell transistors, leading to incorrect data determination and potential errors in storage states.
Innovation Solution
A memory system comprising a semiconductor memory and a memory controller that uses a combination of hard decision and soft decision error correction methods, including Bose Chaudhuri Hocquenghem (BCH) codes, Reed Solomon codes, and low-density parity check (LDPC) codes, along with LLR value calculations and shift reads to determine optimal read voltages for accurate data correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hard decision error correction is used, then the error correction process is simple and fast, but the correction accuracy is insufficient due to threshold voltage variations
Solution Approach 1:
The patent segments the error correction process into two distinct stages: hard decision decoding for rapid initial correction and soft decision decoding for enhanced accuracy. This segmentation allows the system to benefit from both the speed of hard decision and the accuracy of soft decision by applying them in sequence to different aspects of the same data correction task.
Solution Approach 2:
The patent performs preliminary hard decision error correction before proceeding to soft decision error correction. This preliminary action removes easily correctable errors first, reducing the burden on the subsequent soft decision stage and improving overall processing efficiency while maintaining high accuracy.
2Reliability
If soft decision error correction is used, then the correction accuracy is high, but the computational complexity and processing time increase
Solution Approach 1:
The patent segments the error correction process into two distinct stages: hard decision decoding for rapid initial correction and soft decision decoding for enhanced accuracy. This segmentation allows the system to benefit from both the speed of hard decision and the accuracy of soft decision by applying them in sequence to the same data correction task.
Solution Approach 2:
The patent applies partial soft decision correction by first performing hard decision correction to handle the majority of correctable errors, then applying soft decision correction only to remaining problematic cases. This partial application of the more complex soft decision method reduces overall computational burden while maintaining high accuracy.
3Reliability
If multiple error correction codes are implemented, then the error correction capability is enhanced, but the system complexity increases
Solution Approach 1:
The patent merges multiple error correction approaches (hard decision BCH decoding and soft decision LDPC decoding) into a unified error correction system. This merging allows the system to leverage the strengths of different correction codes while managing complexity through a structured sequential processing framework that reuses intermediate results.
Data Source
AI summary
According to one embodiment, a memory system comprising includes a semiconductor memory and a memory controller. The memory controller is configured to obtain first data read from the semiconductor memory using a first voltage, obtain second data read from the semiconductor memory using a second voltage, calculate a first value for a first section of the first data using the first data and the second data, calculate a second value for a second section of the first data using the first data and the second data, calculate a third value for a third section of the first data using the first data and the second data, and correct an error of the first data using the first to third values.