Memory Controller LLR Sign Reversal for LDPC Hard Errors
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Solution Overview
Problem
Low-density parity-check (LDPC) codes face inefficiencies and failures in error correction decoding due to hard errors, leading to performance degradation in memory systems.
Innovation Solution
A memory controller employing an iterative decoding scheme with a mapper, variable node update module, check node update module, syndrome checker, and reversal determiner to convert read values to initial Log Likelihood Ratio (LLR) values, allocate and update values among variable nodes, perform syndrome checks, and reverse the sign of initial LLR values based on message ratios when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative decoding scheme is used for error correction, then error correction performance is improved, but hard errors cause inefficiencies and decoding failures leading to performance degradation
Solution Approach 1:
The patent applies preliminary action by reversing the sign of initial LLR values for variable nodes before the iterative decoding process begins. This pre-processing step anticipates potential hard errors by adjusting the initial state of variable nodes, allowing the decoding to proceed more efficiently without getting stuck in failed iterations. The reversal is determined based on syndromes calculated from the received codeword, enabling the system to proactively correct for expected error patterns.
Solution Approach 2:
The patent changes the parameter of LLR values by reversing their signs under specific conditions. When a variable node's initial LLR value has a different sign from the corresponding syndrome bit, the patent reverses the sign to align with the expected correct value. This parameter modification directly addresses hard errors by correcting the initial state of variable nodes, thereby improving both reliability and decoding efficiency without requiring additional iterative cycles.
2Reliability
If code length is increased in LDPC coding, then error correction performance is improved, but computational complexity per bit increases
Solution Approach 1:
The patent extracts and corrects hard errors before the main iterative decoding process begins by reversing signs of initial LLR values based on syndrome analysis. This extraction of error correction from the main decoding loop reduces the computational burden during iteration, allowing longer code lengths to be processed with acceptable complexity. By handling obvious errors upfront, the system avoids the need for extensive iterative processing of known error patterns.
Solution Approach 2:
The patent performs preliminary error correction by calculating syndromes and reversing signs of initial LLR values before iterative decoding starts. This preliminary action reduces the number of iterations needed for convergence, thereby reducing computational complexity per bit while maintaining the benefits of longer code lengths for improved error correction performance.
3Reliability
If maximum iterations are increased to handle hard errors, then decoding success rate is improved, but processing time increases
Solution Approach 1:
The patent performs preliminary correction of hard errors by reversing signs of initial LLR values based on syndrome analysis before the iterative decoding process begins. This preliminary action resolves many hard errors upfront, reducing the need for additional iterative cycles and thereby decreasing processing time while maintaining high decoding success rates.
Solution Approach 2:
The patent skips unnecessary iterative processing by correcting hard errors in advance through sign reversal. By resolving obvious errors before iteration begins, the system rushes through the preliminary correction phase and can complete decoding in fewer iterations, reducing overall processing time while maintaining high success rates.
Data Source
AI summary
In a memory controller for performing error correction decoding, using an iterative decoding scheme, the memory controller includes a variable node update module for allocating the initial LLR values to variable nodes, and updating values of the variable nodes, using the initial LLR values and Check to Variable (C2V) messages corresponding to the variable nodes in an ith iteration, a syndrome checker for performing a syndrome check, using the values of the variable nodes updated in the ith iteration, and a reversal determiner for determining whether to reverse the sign of an initial LLR value of a target variable node based on a ratio of signs of C2V messages corresponding to the target variable node, when the syndrome check corresponding to the ith iteration fails.