Memory Controller Low-Power Storage Mechanism
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Solution Overview
Problem
Existing power-saving strategies in electronic devices often sacrifice performance, leading to reduced user satisfaction, as they fail to effectively reduce power consumption without compromising functionality.
Innovation Solution
A protocol for entering and exiting a very low power operational state (DEVSLP) is implemented, utilizing a combination of firmware functionality and storage device hardware support, where a memory controller prepares a sleep image, powers down non-volatile memory, and transfers state information to volatile memory, allowing for a deeper power reduction without performance loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional power-saving strategies are implemented, then power consumption is reduced, but performance is sacrificed
Solution Approach 1:
The system dynamically transitions between different operational states (active, low-power, and very low-power DEVSLP states) based on workload requirements. The memory controller and storage device can flexibly adjust their operational mode, allowing the system to optimize between power consumption and performance dynamically rather than being locked into a fixed power-saving mode that sacrifices performance.
Solution Approach 2:
Before entering the very low-power DEVSLP state, the system performs preliminary actions by transferring state information from volatile memory to non-volatile memory and preparing sleep images. This preliminary preparation enables the system to enter a deeper power state without losing operational context, allowing rapid resumption of operations without performance penalty when exiting the low-power state.
2Duration of action of stationary object
If deeper power reduction is implemented, then battery life is extended, but system responsiveness may be compromised
Solution Approach 1:
The system creates copies of critical state information and transfers it from volatile memory to non-volatile memory before entering the DEVSLP state. This copying mechanism ensures that when the system wakes from deep sleep, it can rapidly restore operational state without lengthy initialization sequences, maintaining system responsiveness while enabling deeper power reduction during idle periods.
Solution Approach 2:
Non-volatile memory serves as an intermediary storage medium that bridges the gap between volatile memory and the deep power state. It holds state information during the DEVSLP period, allowing the system to maintain responsiveness by quickly reloading state from this intermediary storage rather than performing full system initialization upon waking.
Data Source
AI summary
Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.