Memory Controller LP2E State Power Management
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Solution Overview
Problem
Existing power management standards, such as ACPI, do not specifically optimize power consumption or performance for specific data processing systems, leading to inefficiencies in managing power states for memory controllers and DRAM systems.
Innovation Solution
The implementation of an enhanced low-power state, referred to as the "LP2E state", which allows memory controllers and physical interface circuits to reduce power consumption by removing operating power and clock signals from most components, while maintaining critical configuration data in an always-on memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If operating power is removed from physical interface circuit to reduce power consumption, then power consumption is reduced, but configuration data storage capability is lost
Solution Approach 1:
The patent divides the physical interface circuit into two separate memory components: volatile memory for configuration data and non-volatile memory for retention. This segmentation allows the volatile memory to be powered down (reducing power consumption) while the non-volatile memory maintains configuration data (preserving reliability).
Solution Approach 2:
The patent introduces an intermediary mechanism (power management circuit and control logic) that coordinates between the volatile and non-volatile memory components. This intermediary manages the transition of configuration data between memory types during power state changes, ensuring data integrity while enabling power savings.
2Reliability
If additional retention flip-flops are added to maintain configuration data, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent uses a copying mechanism where configuration data is replicated from volatile memory to non-volatile memory during power-down transitions. This copying approach replaces the need for complex retention flip-flop circuits with a simpler memory-to-memory transfer process, reducing device complexity while maintaining data retention.
Solution Approach 2:
The patent employs non-volatile memory as a temporary holding mechanism for configuration data during power state transitions. This approach uses simpler, more cost-effective memory technology compared to retention flip-flops, achieving data retention without increasing device complexity.
3Use of energy by moving object
If clock signals are removed from components to reduce power consumption, then power consumption is reduced, but timing parameter precision is degraded
Solution Approach 1:
The patent performs preliminary actions by saving critical timing parameters to non-volatile memory before power-down occurs. This preliminary data preservation ensures that when the system powers back up, the timing parameters can be quickly restored without requiring complex retention circuitry during the powered-off state.
Solution Approach 2:
The patent changes the operational state of timing-critical components by transitioning them between powered and powered-off states based on system activity. Critical timing parameters are preserved through software-based storage and restoration, allowing the hardware to enter low-power states without permanently degrading timing precision.
Data Source
AI summary
A memory accessing circuit includes a memory controller for scheduling accesses to a memory, and a physical interface circuit for driving signals to the memory according to scheduled accesses and having configuration data. The memory controller comprises a memory and is responsive to a low power mode entry signal to save the configuration data in the memory. The physical interface circuit removes operating power from circuitry in the physical interface circuit that stores the configuration data in response to the memory controller completing a save operation.