Memory Controller LPN Translator for Flash Latency Reduction
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Solution Overview
Problem
Flash memory controllers face high read/write latency due to the complex mapping process between logical block addresses and physical page numbers, resulting in firmware overhead and delays.
Innovation Solution
A memory controller and system that allocate a portion of the memory mapped address space to logical physical numbers (LPNs), allowing direct access without additional computation or delays, using a flash translation layer (FTL) mapping table to translate logical addresses to physical page numbers (PPNs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a flash translation layer (FTL) mapping process is used to map logical block addresses to physical page numbers, then data can be stored and retrieved in flash memory, but read/write latency increases due to firmware overhead and multiple mapping steps
Solution Approach 1:
The patent segments the address space into two distinct parts: a lower address space for LPN-to-PPN mapping and an upper address space for LBA-to-LPN mapping. This segmentation allows the CPU to directly access LPNs in the lower address space without going through the FTL mapping process, thereby reducing read/write latency while maintaining the necessary mapping functionality for LBA access.
2Adaptability or versatility
If multiple mapping steps are performed to translate logical block addresses to physical page numbers, then comprehensive address translation is achieved, but firmware overhead increases causing delays
Solution Approach 1:
The patent extracts the LPN-to-PPN mapping function from the general FTL mapping process and implements it as a dedicated, direct mapping mechanism in the lower address space. This extraction allows the CPU to access LPNs directly without invoking the complex FTL firmware, reducing firmware overhead while preserving the adaptability of the system for LBA-to-LPN mapping through the upper address space.
3Productivity
If logical addresses are allocated in the memory mapped address space accessible by CPU, then direct access to LPNs is enabled, but the mapping process becomes simpler and faster
Solution Approach 1:
The patent introduces a new dimension in address space organization by allocating LPNs in the lower address space and LBAs in the upper address space of the memory mapped address space. This dimensional separation allows the CPU to directly access LPNs with simple address translation, improving access speed, while the FTL mapping functionality is preserved for LBA access in the upper address space.
Data Source
AI summary
A memory controller and a memory system including the same are provided. The memory controller includes a memory storing a flash translation layer (FTL) mapping table, which includes a physical page number (PPN) of a flash memory and a logical page number (LPN) corresponding to the PPN; a central processing unit (CPU) accessing a memory mapped address space to which a logical address corresponding to the LPN is allocated; and an LPN translator receiving the logical address from the CPU, extracting an LPN corresponding to the logical address, reading, from the memory, the FTL mapping table corresponding to the extracted LPN, extracting a PPN corresponding to the extracted LPN, and transmitting the extracted PPN to the CPU.