Memory Controller Map Data Transmission for Sequential Access
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Solution Overview
Problem
Current memory systems face inefficiencies in data access operations due to unnecessary L2P conversion and overhead in transmitting map data, which affects performance speed and efficiency, especially in sequential access and prefetch operations.
Innovation Solution
A memory system and method that generates and transmits map data to a host, allowing for direct access operations on physical addresses based on logical information, reducing the need for L2P conversion and optimizing sequential read and prefetch operations by performing these operations in an interleaving manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If map data is transmitted to the host for direct physical address access, then access speed is improved, but communication overhead and memory bandwidth consumption increase
Solution Approach 1:
The patent extracts only the necessary portion of map data (specifically the physical address information corresponding to the requested logical address range) and transmits it to the host, rather than transmitting the entire map data structure. This reduces communication overhead while still enabling the host to perform direct physical address access for the specific data range needed.
2Measurement precision
If L2P conversion is performed for every access request, then address mapping accuracy is maintained, but processing time and system overhead increase
Solution Approach 1:
The patent performs preliminary actions by providing the host with physical address information in advance through map data transmission. This allows the host to directly access physical addresses without performing L2P conversion at the time of each access request, thereby reducing processing time while maintaining address mapping accuracy through the pre-transmitted map data.
3Productivity
If sequential access operations are performed on consecutive physical addresses, then data access efficiency is improved, but read disturbance in memory increases
Solution Approach 1:
The patent applies partial action by performing sequential read operations on only the specific consecutive physical addresses that correspond to the requested logical address range, rather than reading all consecutive physical addresses. This maintains data access efficiency for the needed data while minimizing read disturbance by limiting the scope of sequential reads to only what is necessary.
4Speed
If prefetch operations are performed to improve read performance, then data access speed increases, but unnecessary data retrieval and energy consumption occur
Solution Approach 1:
The patent applies local quality by performing prefetch operations targeted at specific physical address ranges that correspond to the requested logical address information, rather than indiscriminately prefetching data from all locations. This enables improved data access speed for the needed data while avoiding unnecessary data retrieval and associated energy consumption by focusing prefetch operations only on relevant local regions.
Data Source
AI summary
A memory system includes a memory device including a plurality of memory dies that store data, and a controller coupled to the plurality of memory dies through a plurality of channels, and suitable for generating and managing map data in which a logical address of a host is corresponding to a physical address of the memory device, wherein, when logical information on two or more consecutive logical addresses requested to be accessed and physical information on two or more consecutive physical addresses corresponding to the two or more consecutive logical addresses are inputted from the host, the controller sequentially performs access operations on the physical addresses corresponding to the received physical information.