Non-volatile Memory Controller Mapping Cache Optimization
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Solution Overview
Problem
Non-volatile memory systems experience reduced response speed due to structural characteristics that hinder efficient communication with hosts, leading to prolonged processing times for commands and data access.
Innovation Solution
Implementing a non-volatile memory system with a memory controller that stores and manages mapping information between logical and physical addresses, using a mapping information storage unit to cache frequently accessed data, and transmitting size information to optimize command packet ordering and reduce the need for frequent data erasure and programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If mapping information is stored directly in non-volatile memory without caching, then storage capacity is maximized, but access speed decreases due to prolonged processing times
Solution Approach 1:
The patent pre-loads mapping information from non-volatile memory into a mapping information storage unit (cache) before it is needed for data access operations. This preliminary action ensures that frequently accessed mapping information is already available in faster storage, eliminating the need to retrieve it from non-volatile memory during actual data operations, thus reducing processing time while maintaining storage capacity.
Solution Approach 2:
The patent introduces a mapping information storage unit as an intermediary component between the host and non-volatile memory. This intermediary caches mapping information, allowing the system to resolve address mappings quickly without directly accessing non-volatile memory for every data access operation, thereby improving response speed while preserving the storage capacity of the non-volatile memory.
2Speed
If mapping information is cached in a storage unit, then access speed increases, but device complexity increases due to additional components
Solution Approach 1:
The mapping information storage unit is designed to serve multiple functions: it caches mapping information for fast access, stores size information about mapping data groups, and provides the basis for command packet ordering. By making this component multi-functional, the patent reduces the need for separate dedicated components for each function, thereby limiting the increase in device complexity while still achieving improved access speed.
3Productivity
If commands are processed in received order, then ease of operation is maintained, but productivity decreases due to inefficient data access patterns
Solution Approach 1:
The patent implements a feedback mechanism where the host receives size information about mapping data groups from the memory controller, uses this information to reorder commands in command packets, and sends the reordered commands back to the memory system. This feedback loop enables the system to optimize data access patterns by grouping commands that access data within the same mapping data group, improving productivity while maintaining operational simplicity through automated reordering based on received size information.
Data Source
AI summary
A nonvolatile memory system includes a memory controller for copying a mapping data group including logical-physical address mapping information regarding user data from a nonvolatile memory to a mapping information storage unit, and transmit size information regarding the mapping data group to a host. The host may receive size information regarding the mapping data group from the nonvolatile memory system, and determine the order of commands to be transmitted to the nonvolatile memory based on the size information regarding the mapping data group.