Memory Controller Mapping for Non-Power-of-Two Arrays
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Solution Overview
Problem
Existing memory access techniques are inefficient when using a non-power of two number of memory controllers, as they fail to evenly distribute memory access requests, leading to increased latency and locality issues.
Innovation Solution
A system and method that divide memory addresses into a plurality of regions and map each memory controller to a subset of these regions, where each subset includes a power of two number of regions, ensuring even distribution of memory access requests across memory controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If specialized memory access patterns are used for power of two memory controllers, then memory access requests are evenly distributed, but the system is limited to specific numbers of memory controllers
Solution Approach 1:
The memory space is divided into multiple regions, and each memory controller is mapped to a specific subset of these regions. This segmentation allows the system to handle non-power-of-two numbers of memory controllers while maintaining even distribution of access requests.
Solution Approach 2:
The patent changes the parameter of memory controller count from being restricted to power-of-two values to accepting any integer value. This is achieved by modifying the address mapping scheme to accommodate variable numbers of controllers through region-based allocation.
2Power
If memory controllers access memory locations close to one another, then access bandwidth increases, but latency increases due to locality issues
Solution Approach 1:
By dividing the memory space into regions and distributing them across multiple memory controllers, the system achieves both high bandwidth (through parallel access) and low latency (by spreading access patterns across different controllers, avoiding concentration on a single controller).
Data Source
AI summary
A system including a memory space that is accessible for reading or writing data, N memory controllers, N being an integer that is greater than one and is not a power of two, and one or more processors configured to assign addresses of the memory space to M regions and map each of the N memory controllers to a subset of the M regions. Each subset of the M regions may include exactly J regions, J being less than M and a power of two. More than one memory controller may be mapped to each region of the plurality of M regions. The same number of memory controllers may be mapped to each region of the M regions.