Memory Controller Mapping Table Optimization
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Solution Overview
Problem
In flash memory storage systems, the simultaneous need to perform erasing operations and valid data merging procedures often results in excessive loading of the same logical address-physical address mapping table, leading to prolonged response times for the host system due to the independence of these mechanisms.
Innovation Solution
A method where the memory management circuit selectively loads and updates logical address-physical address mapping tables separately for erasing operations and data merging procedures, preventing repeated loading and optimizing the process by identifying and copying valid data from one physical erasing unit to another.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory management circuit performs erasing operations and valid data merging procedures independently and simultaneously, then both operations can be executed, but the response time for the host system is prolonged due to repeated loading of the same logical address-physical address mapping table
Solution Approach 1:
The patent combines the erasing operation and valid data merging procedure into a single integrated operation. When the memory management circuit determines that a physical erasing unit needs erasing, it simultaneously performs the erasing operation and the valid data merging procedure in one process, rather than executing them as separate independent operations. This integration eliminates the repeated loading of the logical address-physical address mapping table that occurs when operations are performed independently, thereby reducing the response time for the host system while maintaining both operational functions.
2Reliability
If the memory management circuit loads the logical address-physical address mapping table for each operation, then the operation can be performed accurately, but the repeated loading causes excessive delay
Solution Approach 1:
The patent loads the logical address-physical address mapping table once before initiating the combined erasing and merging operation, rather than loading it separately for each operation. This preliminary loading ensures that the mapping information is available for both the erasing operation and the valid data merging procedure, maintaining mapping accuracy while avoiding the excessive delay caused by repeated loading. The mapping table is loaded into the buffer memory in advance and reused throughout the integrated operation.
3Productivity
If the erasing operation is performed before valid data merging, then the physical erasing unit can be reused, but data loss occurs if valid data is not preserved
Solution Approach 1:
The patent inverts the traditional sequence by performing the valid data merging procedure simultaneously with the erasing operation, rather than completing the merge before erasing. The memory management circuit identifies valid data in the physical erasing unit, copies it to a destination physical erasing unit, and performs the erasing operation on the source unit all as part of the same integrated process. This inversion ensures that valid data is preserved through the merging operation while the erasing operation can proceed without waiting for separate data transfer operations, maintaining both data safety and erasing efficiency.
Data Source
AI summary
A valid data merging method, a memory controller and a memory storage apparatus are provided. The method includes: selecting a first physical erasing unit, and loading a first logical address-physical address mapping table according to a physical address-logical address mapping table. The method also includes: updating the first logical address-physical address mapping table according to the physical address-logical address mapping table, and identifying valid data in the first physical erasing unit according to the physical address-logical address mapping table and the first logical address-physical address mapping table. The method further includes: storing the first logical address-physical address mapping table, copying the valid data to a second physical erasing unit, and performing an erasing operation for the first physical erasing unit.