Memory Controller Address Mapping Update Management

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Solution Overview

Problem

Memory systems, such as SSDs with NAND flash memory, face data loss and operational disruptions due to communication interruptions between the host and memory system, as they rely on host memory buffers for logical-to-physical address mapping updates, which are not reliably stored when connections are lost.

Innovation Solution

A memory system with a controller that stores address mapping information in nonvolatile memory and updates data in a second memory, transmitting this data to the host when a threshold is reached, allowing for continued operation even during communication interruptions by using host memory buffers as temporary storage areas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the memory system uses host memory buffer for LUT updates, then the productivity is improved, but the reliability deteriorates when communication is interrupted

Engineering Contradiction:
ImproveLUT update speedVSAvoiddata loss risk
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The memory system proactively stores backup LUT data in its own buffer memory before communication interruptions occur. This preliminary action ensures that when communication is interrupted, the LUT data is already preserved locally and can be restored without loss, thus maintaining reliability while still utilizing host memory buffer for normal operations to improve productivity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system creates a cushion of backup LUT data in the memory system's buffer memory as a protective measure against communication interruptions. This beforehand cushioning allows the system to withstand communication failures without losing LUT data, resolving the contradiction between using host memory buffer for speed and protecting against data loss

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If the memory system stores LUT in nonvolatile memory, then the reliability is improved, but the speed of address mapping deteriorates

Engineering Contradiction:
Improvedata persistenceVSAvoidaddress mapping speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The LUT storage function is segmented into multiple locations: host memory buffer for primary storage, memory system buffer memory for backup, and nonvolatile memory for persistent storage. This segmentation allows the system to access LUT data from the fastest available location (host or system buffer) for speed while ensuring persistence in nonvolatile memory, thus resolving the contradiction between reliability and speed

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory system's buffer memory acts as an intermediary between the nonvolatile memory and the host memory buffer. It provides backup copies of LUT data that can be quickly accessed during communication interruptions, serving as a mediator that enables fast access while maintaining the reliability benefits of nonvolatile storage

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12189537B2Memory system that manages update of address mapping information and method for controlling the same
Publication Date: 2025.01.07 KIOXIA CORP
  • US12189537B2 patent drawing
  • US12189537B2 patent drawing
  • US12189537B2 patent drawing

AI summary

A memory system includes a first memory, a second memory, and a controller. The controller is configured to store address mapping information in the first memory, store, in the second memory, a mapping update data that is generated each time data writing to the first memory is performed, and upon an amount of mapping update data that have not been transmitted to the host reaching a threshold, transmit the address mapping information in the first memory and the mapping update data in the second memory to the host and cause the host to store updated address mapping information in a third memory in the host. The controller is configured to perform address mapping using the address mapping information in the first memory and the mapping update data in the second memory when connection with the host is lost.