Memory Controller Mask Signal Timing Calibration
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Solution Overview
Problem
High data rates in contemporary memory systems, such as DDR3, face challenges in write data eye training due to system jitter, PCB trace skew, and DRAM uncertainty, making existing automated self-calibration systems unreliable.
Innovation Solution
A method and memory controller that perform mask signal and data signal training procedures to determine timing offsets, ensuring accurate alignment of data strobe, mask, and data signals, thereby improving write eye opening and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If automated self-calibration systems are used for write data eye training, then calibration process is simplified, but reliability deteriorates due to system jitter, PCB trace skew and DRAM uncertainty at high data rates
Solution Approach 1:
The patent implements feedback mechanisms by reading back written data values and comparing them with expected values to detect timing errors. The system uses the mask signal feedback to identify which data values were successfully written and which were masked, then adjusts timing offsets based on this feedback to achieve reliable calibration at high data rates
Solution Approach 2:
The patent performs preliminary timing offset calibration before actual data transmission. It uses preliminary write operations with known patterns and preliminary read operations to determine timing offsets, establishing a foundation for reliable high-speed operation before normal data transfer begins
2Productivity
If data rate is increased to achieve higher productivity, then throughput is improved, but write data eye training becomes unreliable due to increased jitter and skew effects
Solution Approach 1:
The patent implements dynamic timing adjustment by allowing timing offsets to be adjusted based on detected conditions. The system dynamically modifies timing parameters during calibration and operation to compensate for jitter and skew effects that increase with data rate, maintaining reliability while achieving high throughput
Solution Approach 2:
The patent changes timing parameters (timing offsets) based on detected conditions during calibration. It adjusts phase relationships between clock, data, and mask signals by modifying timing parameters to optimize eye opening and maintain reliable operation at high data rates
3Reliability
If timing calibration is performed to improve write eye opening, then setup and hold margins are balanced, but additional calibration steps increase process complexity
Solution Approach 1:
The patent merges mask signal calibration with data signal calibration into a unified process. By using the mask signal to identify valid data write positions and combining these calibration steps, the system achieves comprehensive timing alignment without requiring completely separate calibration procedures, managing complexity while improving eye opening
Data Source
AI summary
A memory controller transmits a data signal, a data strobe signal and a mask signal to a memory, wherein each transition of the data strobe signal indicates a sample point for the data signal and the mask signal indicates a validity of the data signal. A mask signal training procedure is carried out comprising three steps. Writing first and second values to the memory for a predetermined plurality of transitions of the data strobe signal with the mask signal set to indicate that the first data signal is valid and the second data signal is valid except for a selected transition of the predetermined plurality. Reading from the memory for the predetermined plurality of transitions of the data strobe signal. Determining a timing offset for the mask signal for which the value read at the selected transition matches the first value.