Memory Controller Defect Detection via Machine Learning
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Solution Overview
Problem
Current memory controllers face inefficiencies in defect detection, as they rely on standard test patterns and modes, which can lead to prolonged defect identification times and reduced reliability, especially when dealing with varying voltage and time conditions.
Innovation Solution
A memory controller with a test controller and machine learning processor that selects target patterns and modes to optimize defect detection, using a combination of test signals with different voltage and time conditions, and calculates defect values to identify accelerated defect modes, thereby enhancing detection speed and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard test patterns and modes are used for defect detection, then the testing process is simple and reliable, but the defect identification time is prolonged and detection performance is reduced
Solution Approach 1:
The patent applies parameter changes by varying voltage and time conditions of test signals across multiple test modes. The machine learning processor analyzes test results under different parameters (voltage levels, time intervals) to identify defect acceleration modes, thereby reducing detection time while maintaining reliability through systematic parameter variation.
Solution Approach 2:
The patent replaces traditional mechanical/standard testing approaches with a machine learning-based system. The machine learning processor automatically selects optimal test patterns and identifies defect acceleration modes based on test result information, substituting manual or fixed procedural testing with intelligent adaptive testing that reduces time loss.
2Productivity
If multiple test patterns and modes are used to improve defect detection performance, then detection speed and reliability are enhanced, but the test complexity and processing requirements increase
Solution Approach 1:
The machine learning processor performs self-service by automatically selecting target test patterns from multiple available patterns and identifying defect acceleration modes based on test result information. This automation reduces the need for manual configuration and management of complex test parameters, enabling high detection speed without proportional increase in operational complexity.
Solution Approach 2:
The system implements feedback through the machine learning processor that analyzes test result information from multiple test modes and uses this feedback to identify defect acceleration modes. The feedback mechanism allows the system to adaptively optimize test selection based on accumulated data, improving detection speed while managing complexity through learned patterns rather than exhaustive testing.
Data Source
AI summary
A memory controller includes a test controller, a test information storage, and a machine learning processor. The test controller performs a test on a memory device using a target pattern selected from among a plurality of test patterns in each of a plurality of test modes in which voltage and time conditions of test signals are set differently. The test information storage stores test result information including values associated with fail bits of the memory device measured in the test. The machine learning processor detects a defect acceleration mode in which a defect of the memory device is accelerated, among the plurality of test modes, in the test performed using the target pattern on the basis of the test result information.