Memory Controller Decoding for MLC Read Error Correction
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Solution Overview
Problem
Multi-level cell (MLC) non-volatile memory devices face reliability issues due to overlapping threshold voltage distributions, leading to increased read failure rates and data errors as the number of bits programmed in each memory cell increases, causing neighboring distributions to overlap and making it difficult to accurately read data.
Innovation Solution
A memory controller and semiconductor memory system that employs a decoding method using internal and outer parities, specifically through Tensor Product Codes and BCH codes, to detect and correct errors in memory cells, ensuring reliable and quick data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data is programmed in each memory cell to increase storage capacity, then data storage capacity is improved, but read reliability deteriorates due to overlapping threshold voltage distributions
Solution Approach 1:
The patent segments the error correction process into two distinct stages: inner decoding using Tensor Product Codes for initial error correction, and outer decoding using BCH codes for residual error correction. This segmentation allows each decoding stage to specialize in correcting specific types of errors, thereby maintaining high read reliability even when multiple bits per cell increase storage capacity
Solution Approach 2:
The patent employs a composite error correction code structure combining Tensor Product Codes (inner code) and BCH codes (outer code). This composite approach leverages the strengths of both coding schemes: TPC handles burst errors and intra-cell errors effectively, while BCH code provides additional protection against residual errors, together achieving superior reliability for multi-bit per cell storage
2Quantity of substance
If the number of bits programmed in each memory cell increases, then storage density is improved, but the distance between threshold voltage distributions decreases causing overlap
Solution Approach 1:
The patent transitions from single-level cell (SLC) one-dimensional threshold voltage distinction to multi-level cell (MLC) multi-dimensional threshold voltage distributions. By programming multiple bits per cell, the system creates 2^k distinct threshold voltage levels (e.g., 8 levels for 3-bit MLC), effectively adding dimensions to the storage space and increasing storage density while maintaining distinguishability through careful voltage window management
Solution Approach 2:
The patent changes the parameter of bits per cell from 1 (SLC) to multiple bits (MLC with 2 or more bits per cell). This parameter change increases storage density by a factor of 2^k, but requires corresponding changes in read voltage selection and error correction strategies to handle the reduced margin between adjacent threshold voltage distributions
3Device complexity
If conventional single decoding method is used, then device complexity is reduced, but error correction capability is insufficient for MLC memory
Solution Approach 1:
The patent segments the decoding function into two separate decoding units: an inner decoder implementing Tensor Product Code and an outer decoder implementing BCH code. This segmentation distributes the error correction burden across two specialized decoders, achieving superior error correction capability while keeping each individual decoder relatively simple and manageable
Solution Approach 2:
The patent applies preliminary error correction through the inner TPC decoder before the outer BCH decoder processes the data. This preliminary action removes the majority of errors (particularly burst errors and intra-cell errors) in the first stage, reducing the error burden on the second stage and enabling the outer decoder to focus on correcting residual errors with simpler operations
Data Source
AI summary
An operation method of a memory controller may include performing a first decoding operation to a message of an internal region included in a codeword received from a semiconductor memory device by using an internal parity, wherein the message and the internal parity are included in the internal region in a matrix form; and performing a second decoding operation to the internal region, to which the first decoding operation is performed, by using an outer parity of an outer region.